48-Bit LVDS
DS90CR481, DS90CR482
www.ti.com
SNLS137D – NOVEMBER 2000 – REVISED APRIL 2013
DS90CR481 / DS90CR482 48-Bit LVDS Chann...
Description
DS90CR481, DS90CR482
www.ti.com
SNLS137D – NOVEMBER 2000 – REVISED APRIL 2013
DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz
Check for Samples: DS90CR481, DS90CR482
FEATURES
1
2 3.168 Gbits/sec Bandwidth with 66 MHz Clock
5.376 Gbits/sec Bandwidth with 112 MHz Clock
65 - 112 MHz Input Clock Support
LVDS SER/DES Reduces Cable and Connector Size
Pre-Emphasis Reduces Cable Loading Effects
Optional DC Balance Encoding Reduces ISI Distortion
Cable Deskew of +/−1 LVDS Data Bit Time (up to 80 MHz Clock Rate)
5V Tolerant TxIN and Control Input Pins
Flow Through Pinout for Easy PCB Design
+3.3V Supply Voltage
Transmitter Rejects Cycle-to-Cycle Jitter
Conforms to ANSI/TIA/EIA-644-1995 LVDS Standard
DESCRIPTION
The DS90CR481 transmitter converts 48 bits of CMOS/TTL data into eight LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a ninth LVDS link. Every cycle of the transmit clock 48 bits of input data are sampled and transmitted. The DS90CR482 receiver converts the LVDS data streams back into 48 bits of LVCMOS/TTL data. At a transmit clock frequency of 112MHz, 48 bits of TTL data are transmitted at a rate of 672Mbps per LVDS data channel. Using a 112MHz clock, the data throughput is 5.38Gbit/s (672Mbytes/s). At a transmit clock frequency of 112MHz, 48 bits of TTL data are transmitted at a rate of 672Mbps per LVDS data channel. Using a 66MHz clock,...
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