DS90CR486 Link Deserializer Datasheet

DS90CR486 Datasheet, PDF, Equivalent


Part Number

DS90CR486

Description

133MHz 48-Bit Channel Link Deserializer

Manufacture

etcTI

Total Page 22 Pages
Datasheet
Download DS90CR486 Datasheet


DS90CR486
DS90CR486
www.ti.com
SNLS149C – FEBRUARY 2003 – REVISED MARCH 2013
DS90CR486 133MHz 48-Bit Channel Link Deserializer (6.384 Gbps)
Check for Samples: DS90CR486
FEATURES
1
2 Up to 6.384 Gbps Throughput
• 66MHz to 133MHz Input Clock Support
• Reduces Cable and Connector Size and Cost
• Cable Deskew Function
• DC Balance Reduces ISI Distortion
• For Point-to-Point Backplane or Cable
Applications
• Low Power, 890 mW Typ at 133MHz
• Flow through Pinout for Easy PCB Design
• +3.3V Supply Voltage
• 100-pin TQFP Package
• Conforms to TIA/EIA-644-A-2001 LVDS
Standard
DESCRIPTION
The DS90CR486 receiver converts eight Low Voltage
Differential Signaling (LVDS) data streams back into
48 bits of LVCMOS/LVTTL data. Using a 133MHz
clock, the data throughput is 6.384Gbit/s
(798Mbytes/s).
The multiplexing of data lines provides a substantial
cable reduction. Long distance parallel single-ended
buses typically require a ground wire per active signal
(and have very limited noise rejection capability).
Thus, for a 48-bit wide data and one clock, up to 98
conductors are required. With this Channel Link
chipset as few as 19 conductors (8 data pairs, 1 clock
pair and a minimum of one ground) are needed. This
provides an 80% reduction in interconnect width,
which provides a system cost savings, reduces
connector physical size and cost, and reduces
shielding requirements due to the cables' smaller
form factor.
The DS90CR486 deserializer is improved over prior
generations of Channel Link devices and offers
higher bandwidth support and longer cable drive with
three areas of enhancement. To increase bandwidth,
the maximum clock rate is increased to 133 MHz and
8 serialized LVDS outputs are provided. Cable drive
is enhanced with a user selectable pre-emphasis (on
DS90CR485) feature that provides additional output
current during transitions to counteract cable loading
effects. Optional DC balancing on a cycle-to-cycle
basis, is also provided to reduce ISI (Inter-Symbol
Interference). With pre-emphasis and DC balancing,
a low distortion eye-pattern is provided at the receiver
end of the cable. A cable deskew capability has been
added to deskew long cables of pair-to-pair skew.
These three enhancements allow long cables to be
driven.
The DS90CR486 is intended to be used with the
DS90CR485 Channel Link Serializer. It is also
backward compatible with serializers DS90CR481
and DS90CR483. The DS90CR486 is footprint
compatible with the DS90CR484.
The chipset is an ideal solution to solve EMI and
interconnect size problems for high-throughput point-
to-point applications.
For more details, please refer to the APPLICATIONS
INFORMATION section of this datasheet.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated

DS90CR486
DS90CR486
SNLS149C – FEBRUARY 2003 – REVISED MARCH 2013
Generalized Block Diagram
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)(2)
Supply Voltage (VCC)
LVCMOS/LVTTL Output Voltage
LVDS Receiver Input Voltage
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 4 sec.)
Maximum Package Power Dissipation Capacity @ 25°C 100 TQFP Package:
Package Derating:
ESD Rating: (HBM, 1.5k, 100pF)
ESD Rating: (EIAJ, 0, 200pF)
Value
0.3 to +3.6
0.3 to (VCC + 0.3)
0.3 to +3.6
+150
65 to +150
+260
2.9
23.8 mW/°C above +25°C
>2
> 200
Unit
V
V
V
°C
°C
°C
W
kV
V
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the device should be operated at these limits. “Electrical Characteristics” specify conditions for device operation.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Recommended Operating Conditions
Supply Voltage (VCC)
Operating Free Air Temperature (TA)
Receiver Input Range
Supply Noise Voltage (VCC)
Clock Rate
Min Nom
3.14 3.3
10 +25
0
66
Max
3.46
+70
2.4
100
133
Units
V
°C
V
mVp-p
MHz
2 Submit Documentation Feedback
Product Folder Links: DS90CR486
Copyright © 2003–2013, Texas Instruments Incorporated


Features DS90CR486 www.ti.com SNLS149C – FEBR UARY 2003 – REVISED MARCH 2013 DS90C R486 133MHz 48-Bit Channel Link Deseria lizer (6.384 Gbps) Check for Samples: D S90CR486 FEATURES 1 •2 Up to 6.384 G bps Throughput • 66MHz to 133MHz Inpu t Clock Support • Reduces Cable and C onnector Size and Cost • Cable Deskew Function • DC Balance Reduces ISI Di stortion • For Point-to-Point Backpla ne or Cable Applications • Low Power, 890 mW Typ at 133MHz • Flow through Pinout for Easy PCB Design • +3.3V Su pply Voltage • 100-pin TQFP Package Conforms to TIA/EIA-644-A-2001 LVDS Standard DESCRIPTION The DS90CR486 rece iver converts eight Low Voltage Differe ntial Signaling (LVDS) data streams bac k into 48 bits of LVCMOS/LVTTL data. Us ing a 133MHz clock, the data throughput is 6.384Gbit/s (798Mbytes/s). The mult iplexing of data lines provides a subst antial cable reduction. Long distance p arallel single-ended buses typically re quire a ground wire per active signal (and have very limited noise rejection capability)..
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