DS90CR583

OBSOLETE DS90CR583, DS90CR584 www.ti.com SNLS110B – JULY 1997 – REVISED APRIL 2013 DS90CR583/DS90CR584 LVDS 24-Bit Color Flat Panel Display (FPD) Link— 65 MHz Check for Samples: DS90CR583, DS90CR584 FEATURES 1 2 20 to 65 MHz Shift clk Support Up to 227 Mbytes/s Bandwidth Cable Size is Reduced to Save Cost 290 mV Swing LVDS Devices for Low EMI Low Power CMOS Design (< 550 mW typ) Power-Down Mode Saves Power (< 0.25 mW) PLL Requires No External Components Low Profile 56-lead TSSOP Package Rising Edge Data Strobe Compatible with TIA/EIA-644 LVDS Standard Single Pixel Per Clock XGA (1024 x 768) Supports VGA, SVGA, XGA and Higher 1.8 Gbps Throughput DESCRIPTION The DS90CR583 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CR584 receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 4 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY, CONTROL) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 227 Mbytes per second. These devices are offered with rising edge data strobes for convenient interface with a variety of graphics and LCD panel controllers. ...