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DS1220AB Dataheets PDF



Part Number DS1220AB
Manufacturers Maxim Integrated
Logo Maxim Integrated
Description 16k Nonvolatile SRAM
Datasheet DS1220AB DatasheetDS1220AB Datasheet (PDF)

19-5580; Rev 10/10 www.maxim-ic.com FEATURES  10 years minimum data retention in the absence of external power  Data is automatically protected during power loss  Directly replaces 2k x 8 volatile static RAM or EEPROM  Unlimited write cycles  Low-power CMOS  JEDEC standard 24-pin DIP package  Read and write access times of 100 ns  Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time  Full ±10% VCC operating range (DS1220AD)  .

  DS1220AB   DS1220AB



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19-5580; Rev 10/10 www.maxim-ic.com FEATURES  10 years minimum data retention in the absence of external power  Data is automatically protected during power loss  Directly replaces 2k x 8 volatile static RAM or EEPROM  Unlimited write cycles  Low-power CMOS  JEDEC standard 24-pin DIP package  Read and write access times of 100 ns  Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time  Full ±10% VCC operating range (DS1220AD)  Optional ±5% VCC operating range (DS1220AB)  Optional industrial temperature range of -40°C to +85°C, designated IND DS1220AB/AD 16k Nonvolatile SRAM PIN ASSIGNMENT A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 VCC 23 A8 22 A9 21 WE 20 OE 19 A10 18 CE 17 DQ7 16 DQ6 15 DQ5 14 DQ4 13 DQ3 24-Pin ENCAPSULATED PACKAGE 720-mil EXTENDED PIN DESCRIPTION A0-A10 DQ0-DQ7 - Address Inputs - Data In/Data Out CE - Chip Enable WE - Write Enable OE VCC GND - Output Enable - Power (+5V) - Ground DESCRIPTION The DS1220AB and DS1220AD 16k Nonvolatile SRAMs are 16,384-bit, fully static, nonvolatile SRAMs organized as 2048 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. The NV SRAMs can be used in place of existing 2k x 8 SRAMs directly conforming to the popular bytewide 24-pin DIP standard. The devices also match the pinout of the 2716 EPROM and the 2816 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. 1 of 8 READ MODE DS1220AB/AD The DS1220AB and DS1220AD execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 11 address inputs (A0-A10) defines which of the 2048 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing that the CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is either tCO for CE or tOE for OE rather than address access. WRITE MODE The DS1220AB and DS1220AD execute a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR ) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE will disable the outputs in tODW from its falling edge. DATA RETENTION MODE The DS1220AB provides full functional capability for VCC greater than 4.75 volts and write protects by 4.5V. The DS1220AD provides full functional capability for VCC greater than 4.5 volts and write protects by 4.25V. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write protect themselves, all inputs become “don’t care,” and all outputs become high impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1220AB and 4.5 volts for the DS1220AD. FRESHNESS SEAL Each DS1220 device is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level of greater than VTP, the lithium energy source is enabled for battery backup operation. 2 of 8 ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground Operating Temperature Range Commercial: Industrial: Storage Temperature Lead Temperature (soldering, 10s) Note: EDIP is wave or hand soldered only. DS1220AB/AD -0.3V to +6.0V 0°C to +70°C -40°C to +85°C -40°C to +85°C +260°C This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specificati.


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