Document
19-5614; Rev 11/10
www.maxim-ic.com
DS1270W 3.3V 16Mb Nonvolatile SRAM
FEATURES
Five years minimum data retention in the
absence of external power Data is automatically protected during power
loss Unlimited write cycles Low-power CMOS operation Read and write access times of 100ns Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time Optional industrial (IND) temperature range
of -40°C to +85°C
PIN ASSIGNMENT
NC A20 A18 A16 A14 A12
A7 A6 A5 A4 A3 A2
A1
A0 DQ0
DQ1
DQ2
GND
1 2 3 4 5 6 7 8 9 10 11 12
13
14
15
16
17
18
36 VCC 35 A19 34 NC 33 A15 32 A17 31 WE 30 A13 29 A8 28 A9 27 A11 26 OE
25 A10
24 CE
23 DQ7 22 DQ6
21 DQ5
20 DQ4
19 DQ3
36-Pin Encapsulated Package 740mil Extended
PIN DESCRIPTION
A0–A20
- Address Inputs
DQ0–DQ7
- Data In/Data Out
CE - Chip Enable
WE - Write Enable
OE - Output Enable
VCC GND
- Power (+3.3V) - Ground
NC - No Connect
DESCRIPTION
The DS1270W 16Mb nonvolatile (NV) SRAMs are 16,777,216-bit, fully static, NV SRAMs organized as 2,097,152 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry that constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. There is no limit on the number of write cycles that can be executed, and no additional support circuitry is required for microprocessor interfacing.
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DS1270W
READ MODE
The DS1270 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 21 address inputs (A0–A20) defines which of the 2,097,152 bytes of data is accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later-occurring signal ( CE or OE ) and the limiting parameter is either tCO for CE or tOE for OE rather than tACC.
WRITE MODE
The DS1270 devices execute a write cycle whenever WE and CE signals are active (low) after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active), then WE will disable the outputs in tODW from its falling edge.
DATA-RETENTION MODE
The DS1270W provides full-functional capability.