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Reference Design
AM4372, AM4376, AM4377, AM4378, AM4379
SPRS851E – JUNE 2014 – REVISED JANUARY 2019
AM437x Sitara™ Processors
1 Device Overview
1.1 Features
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• Highlights – Sitara™ ARM® Cortex®-A9 32-Bit RISC Processor With Processing Speed up to 1000 MHz
– NEON™ SIMD Coprocessor and Vector Floating Point (VFPv3) Coprocessor
– 32KB of Both L1 Instruction and Data Cache
– 256KB of L2 Cache or L3 RAM
– 32-Bit LPDDR2, DDR3, and DDR3L Support
– General-Purpose Memory Support (NAND, NOR, SRAM) Supporting up to 16-Bit ECC
– SGX530 Graphics Engine
– Display Subsystem
– Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRUICSS)
– Real-Time Clock (RTC)
– Up to Two USB 2.0 High-Speed Dual-Role (Host or Device) Ports With Integrated PHY
– 10, 100, and 1000 Ethernet Switch Supporting up to Two Ports
– Serial Interfaces:
– Two Controller Area Network (CAN) Ports
– Six UARTs, Two McASPs, Five McSPIs, Three I2C Ports, One QSPI, and One HDQ or 1-Wire
– Security
– Crypto Hardware Accelerators (AES, SHA, RNG, DES, and 3DES)
– Secure Boot (Avaliable Only on AM437x High-Security [AM437xHS] Devices)
– Two 12-Bit Successive Approximation Register (SAR) ADCs
– Up to Three 32-Bit Enhanced Capture (eCAP) Modules
– Up to Three Enhanced Quadrature Encoder Pulse (eQEP) Modules
– Up to Six Enhanced High-Resolution PWM (eHRPWM) Modules
• MPU Subsystem
– ARM Cortex-A9 32-Bit RISC Microprocessor With Processing Speed up to 1000 MHz
– 32KB of Both L1 Instruction and Data Cache
– 256KB of L2 Cache (Option to Configure as L3 RAM)
– 256KB of On-Chip Boot ROM
– 64KB of On-Chip RAM
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– Secure Control Module (SCM) (Avaliable Only on AM437xHS Devices)
– Emulation and Debug
– JTAG
– Embedded Trace Buffer
– Interrupt Controller
• On-Chip Memory (Shared L3 RAM)
– 256KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
– Accessible to All Masters
– Supports Retention for Fast Wakeup
– Up to 512KB of Total Internal RAM (256KB of ARM Memory Configured as L3 RAM + 256KB of OCMC RAM)
• External Memory Interfaces (EMIFs)
– DDR Controllers:
– LPDDR2: 266-MHz Clock (LPDDR2-533 Data Rate)
– DDR3 and DDR3L: 400-MHz Clock (DDR800 Data Rate)
– 32-Bit Data Bus
– 2GB of Total Addressable Space
– Supports One x32, Two x16, or Four x8 Memory Device Configurations
• General-Purpose Memory Controller (GPMC)
– Flexible 8- and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, and SRAM)
– Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
– Uses Hamming Code to Support 1-Bit ECC
• Error Locator Module (ELM)
– Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH Algorithm
– Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH Algorithms
• Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) – Supports Protocols such as EtherCAT®, PROFIBUS®, PROFINET®, and EtherNet/IP™, EnDat 2.2, and More
– Two Programmable Real-Time Units (PRUs) Subsystems With Two PRU Cores Each
– Each Core is a 32-Bit Load and Store RISC Processor Capable of Running at 200 MHz
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
AM4372, AM4376, AM4377, AM4378, AM4379
SPRS851E – JUNE 2014 – REVISED JANUARY 2019
– 12KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Instruction RAM With Single-Error Detection (Parity)
– 8KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Data RAM With Single-Error Detection (Parity)
– Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
– Enhanced GPIO Module Provides Shift-In and Shift-Out Support and Parallel Latch on External Signal
– 12KB (PRU-ICSS1 Only) of Shared RAM With Single-Error Detection (Parity)
– Three 120-Byte Register Banks Accessible by Each PRU
– Interrupt Controller Module (INTC) for Handling System Input Events
– Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
– Peripherals Inside the PRU-ICSS
– One UART Port With Flow Control Pins, Supports up to 12 Mbps
– One eCAP Module
– Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
– One MDIO Port
– Industrial Communication is Supported by Two PRU-ICSS Subsystems
• Power, Reset, and Clock Management (PRCM) Module
– Controls the Entry and Exit of Deep-Sleep Modes
– Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
– Clocks
– Integrated High-Frequency Oscillator Used to Generate a Reference Clock (19.2, 24, 25, and 26 MHz) for Various System and Peripheral Clocks
– Supports Individual Clock E.