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LM27222
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SNVS306B – SEPTEMBER 2004 – REVISED MARCH 2013
LM27222 High-Speed 4.5A Synchronous MOSFET Driver
Check for Samples: LM27222
FEATURES
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•2 Adaptive Shoot-through Protection • 10ns Dead Time • 8ns Propagation Delay • 30ns Minimum On-time • 0.4Ω Pull-down and 0.9Ω Pull-up Drivers • 4.5A Peak Driving Current • MOSFET Tolerant Design • 5µA Quiescent Current • 30V Maximum Input Voltage in Buck
Configuration • 4V to 6.85V Operating Voltage • SOIC-8 and WSON Packages
APPLICATIONS
• High Current Buck And Boost Voltage Converters
• Fast Transient DC/DC Power Supplies • Single Ended Forward Output Rectification • CPU And GPU Core Voltage Regulators
DESCRIPTION
The LM27222 is a dual N-channel MOSFET driver designed to drive MOSFETs in push-pull configurations as typically used in synchronous buck regulators. The LM27222 takes the PWM output from a controller and provides the proper timing and drive levels to the power stage MOSFETs. Adaptive shootthrough protection prevents damaging and efficiency reducing shoot-through currents, thus ensuring a robust design capable of being used with nearly any MOSFET. The adaptive shoot-through protection circuitry also reduces the dead time down to as low as 10ns, ensuring the highest operating efficiency. The peak sourcing and sinking current for each driver of the LM27222 is about 3A and 4.5Amps respectively with a Vgs of 5V. System performance is also enhanced by keeping propagation delays down to 8ns. Efficiency is once again improved at all load currents by supporting synchronous, nonsynchronous, and diode emulation modes through the LEN pin. The minimum output pulse width realized at the output of the MOSFETs is as low as 30ns. This enables high operating frequencies at very high conversion ratios in buck regulator designs. To support low power states in notebook systems, the LM27222 draws only 5µA from the 5V rail when the IN and LEN inputs are low or floating.
Typical Application
VCC 4V to 6.85V
R1 C1
D1
U1
6 VCC
CB
(to controller) 5 LEN
HG
(to controller) 4
LM27222
IN SW
8 GND
LG
3 2 1 7
C2 0.33 PF
VIN Q1 up to 30V
+ C3
L1 VOUT
Q2
+ C4
0.5V to Vin - 0.5V
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.
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PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
LM27222
SNVS306B – SEPTEMBER 2004 – REVISED MARCH 2013
Connection Diagram
SW 1 HG 2 CB 3
IN 4
8 GND 7 LG 6 VCC 5 LEN
Figure 1. Top View SOIC-8 (Package # D0008A) θJA = 172°C/W
or WSON-8 (Package # NGT0008A) θJA = 39°C/W
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Pin # 1 2
3 4
5
6 7
8
Pin Name SW HG
CB IN
LEN
VCC LG
GND
PIN DESCRIPTIONS
Pin Function High-side driver return. Should be connected to the common node of high and low-side MOSFETs. High-side gate drive output. Should be connected to the high-side MOSFET gate. Pulled down internally to SW with a 10K resistor to prevent spurious turn on of the high-side MOSFET when the driver is off. Bootstrap. Accepts a bootstrap voltage for powering the high-side driver. Accepts a PWM signal from a controller. Active High. Pulled down internally to GND with a 150K resistor to prevent spurious turn on of the high-side MOSFET when the controller is inactive. Low-side gate enable. Active High. Pulled down internally to GND with a 150K resistor to prevent spurious turn-on of the low-side MOSFET when the controller is inactive. Connect to +5V supply. Low-side gate drive output. Should be connected to low-side MOSFET gate. Pulled down internally to GND with a 10K resistor to prevent spurious turn on of the low-side MOSFET when the driver is off. Ground.
Block Diagram
VCC
LEN 150k
IN 150k
Logic
Shoot-through Protection
Level Shifter
CB
HG 10k
SW
+
-
LG 10k
GND
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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Copyright © 2004–2013, Texas Instruments Incorporated
LM27222
www.ti.com
SNVS306B – SEPTEMBER 2004 – REVISED MARCH 2013
Absolute Maximum Ratings (1)
VCC to GND CB to GND CB to SW SW to GND (2) LEN, IN, LG to GND HG to GND Junction Temperature Power Dissipation (3) Storage Temperature ESD Susceptibility
Human Body Model
-0.3V to 7V -0.3V to 36V
-0.3V to 7V -2V to 36V -0.3V to VCC + 0.3V ≤ 7V -0.3V to 36V
+150°C 720mW −65° to 150°C
2kV
(1) Absolute Maximum Ratings are limits beyond which damage to the d.