D-TYPE FLIP-FLOPS. SN74AHC16374 Datasheet

SN74AHC16374 FLIP-FLOPS. Datasheet pdf. Equivalent

SN74AHC16374 Datasheet
Recommendation SN74AHC16374 Datasheet
Part SN74AHC16374
Description 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
Feature SN74AHC16374; SN54AHC16374, SN74AHC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS330G – M.
Manufacture etcTI
Datasheet
Download SN74AHC16374 Datasheet




etcTI SN74AHC16374
SN54AHC16374, SN74AHC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS330G – MARCH 1996 – REVISED JANUARY 2000
D Members of the Texas Instruments
Widebus Family
D EPIC(Enhanced-Performance Implanted
CMOS) Process
D Operating Range 2-V to 5.5-V VCC
D 3-State Outputs Drive Bus Lines Directly
D Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
D Flow-Through Architecture Optimizes PCB
Layout
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’AHC16374 devices are 16-bit
edge-triggered D-type flip-flops with 3-state
outputs designed specifically for driving highly
capacitive or relatively low-impedance loads.
They are particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
SN54AHC16374 . . . WD PACKAGE
SN74AHC16374 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 1CLK
47 1D1
46 1D2
45 GND
44 1D3
43 1D4
42 VCC
41 1D5
40 1D6
39 GND
38 1D7
37 1D8
36 2D1
35 2D2
34 GND
33 2D3
32 2D4
31 VCC
30 2D5
29 2D6
28 GND
27 2D7
26 2D8
25 2CLK
These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock
(CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
The SN54AHC16374 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AHC16374 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 2000, Texas Instruments Incorporated
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etcTI SN74AHC16374
SN54AHC16374, SN74AHC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS330G – MARCH 1996 – REVISED JANUARY 2000
FUNCTION TABLE
(each 8-bit flip-flop)
INPUTS
OE CLK D
OUTPUT
Q
LH
H
LL
L
L H or L X
HXX
Q0
Z
logic symbol
1OE
1CLK
2OE
2CLK
1
48
24
25
47
1D1
46
1D2
44
1D3
43
1D4
41
1D5
40
1D6
38
1D7
37
1D8
36
2D1
35
2D2
33
2D3
32
2D4
30
2D5
29
2D6
27
2D7
26
2D8
1EN
C1
2EN
C2
1D
1
2D 2
2
1Q1
3
1Q2
5
1Q3
6
1Q4
8
1Q5
9
1Q6
11
1Q7
12
1Q8
13
2Q1
14
2Q2
16
2Q3
17
2Q4
19
2Q5
20
2Q6
22
2Q7
23
2Q8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
1OE
48
1CLK
47
1D1
C1
1D
2OE 24
25
2CLK
2
1Q1
2D1 36
C1
1D
13
2Q1
To Seven Other Channels
To Seven Other Channels
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265



etcTI SN74AHC16374
SN54AHC16374, SN74AHC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS330G – MARCH 1996 – REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
SN54AHC16374 SN74AHC16374
UNIT
MIN MAX
MIN MAX
VCC Supply voltage
VIH High-level input voltage
VIL Low-level input voltage
VI Input voltage
VO Output voltage
IOH High-level output current
IOL Low-level output current
t/v Input transition rise or fall rate
TA Operating free-air temperature
VCC = 2 V
VCC = 3 V
VCC = 5.5 V
VCC = 2 V
VCC = 3 V
VCC = 5.5 V
VCC = 2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
VCC = 2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
2 5.5
1.5
2.1
3.85
0.5
0.9
1.65
0 5.5
0 VCC
–50
–4
–8
50
4
8
100
20
–55 125
2 5.5 V
1.5
2.1 V
3.85
0.5
0.9 V
1.65
0 5.5 V
0 VCC V
–50 mA
–4
mA
–8
50 mA
4
mA
8
100
ns/V
20
–40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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