16-BIT BUFFERS/DRIVERS. SN54AHC16541 Datasheet

SN54AHC16541 BUFFERS/DRIVERS. Datasheet pdf. Equivalent

SN54AHC16541 Datasheet
Recommendation SN54AHC16541 Datasheet
Part SN54AHC16541
Description 16-BIT BUFFERS/DRIVERS
Feature SN54AHC16541; SN54AHC16541, SN74AHC16541 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS332F – MARCH 1996 – REVIS.
Manufacture etcTI
Datasheet
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Texas Instruments SN54AHC16541
SN54AHC16541, SN74AHC16541
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS332F – MARCH 1996 – REVISED JANUARY 2000
D Members of the Texas Instruments
Widebus Family
D EPIC(Enhanced-Performance Implanted
CMOS) Process
D Operating Range 2-V to 5.5-V VCC
D Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
D Flow-Through Architecture Optimizes PCB
Layout
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’AHC16541 devices are noninverting 16-bit
buffers composed of two 8-bit sections with
separate output-enable signals. For either 8-bit
buffer section, the two output-enable (1OE1 and
1OE2 or 2OE1 and 2OE2) inputs must be low for
the corresponding Y outputs to be active. If either
output-enable input is high, the outputs of that
8-bit buffer section are in the high-impedance
state.
SN54AHC16541 . . . WD PACKAGE
SN74AHC16541 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1OE1
1Y1
1Y2
GND
1Y3
1Y4
VCC
1Y5
1Y6
GND
1Y7
1Y8
2Y1
2Y2
GND
2Y3
2Y4
VCC
2Y5
2Y6
GND
2Y7
2Y8
2OE1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 1OE2
47 1A1
46 1A2
45 GND
44 1A3
43 1A4
42 VCC
41 1A5
40 1A6
39 GND
38 1A7
37 1A8
36 2A1
35 2A2
34 GND
33 2A3
32 2A4
31 VCC
30 2A5
29 2A6
28 GND
27 2A7
26 2A8
25 2OE2
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54AHC16541 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AHC16541 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 8-bit buffer/driver)
INPUTS
OE1 OE2 A
OUTPUT
Y
LLL
L
L LH
H
HXX
Z
XHX
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 2000, Texas Instruments Incorporated
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Texas Instruments SN54AHC16541
SN54AHC16541, SN74AHC16541
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS332F – MARCH 1996 – REVISED JANUARY 2000
logic symbol
1OE1
1OE2
2OE1
2OE2
1
48
24
25
&
EN1
&
EN2
47
1A1
46
1A2
44
1A3
43
1A4
41
1A5
40
1A6
38
1A7
37
1A8
36
2A1
35
2A2
33
2A3
32
2A4
30
2A5
29
2A6
27
2A7
26
2A8
11
12
2
1Y1
3
1Y2
5
1Y3
6
1Y4
8
1Y5
9
1Y6
11
1Y7
12
1Y8
13
2Y1
14
2Y2
16
2Y3
17
2Y4
19
2Y5
20
2Y6
22
2Y7
23
2Y8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1OE1 1
1OE2 48
24
2OE1
2OE2 25
47
1A1
2
1Y1
36
2A1
13 2Y1
To Seven Other Channels
To Seven Other Channels
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265



Texas Instruments SN54AHC16541
SN54AHC16541, SN74AHC16541
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS332F – MARCH 1996 – REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
SN54AHC16541 SN74AHC16541
UNIT
MIN MAX
MIN MAX
VCC Supply voltage
VIH High-level input voltage
VIL Low-level input voltage
VI Input voltage
VO Output voltage
IOH High-level output current
IOL Low-level output current
t/v Input transition rise or fall rate
TA Operating free-air temperature
VCC = 2 V
VCC = 3 V
VCC = 5.5 V
VCC = 2 V
VCC = 3 V
VCC = 5.5 V
VCC = 2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
VCC = 2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
2 5.5
1.5
2.1
3.85
0.5
0.9
1.65
0 5.5
0 VCC
–50
–4
–8
50
4
8
100
20
–55 125
2 5.5 V
1.5
2.1 V
3.85
0.5
0.9 V
1.65
0 5.5 V
0 VCC V
–50 mA
–4
mA
–8
50 mA
4
mA
8
100
ns/V
20
–40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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