Shift Registers. SN74LV595A-EP Datasheet

SN74LV595A-EP Registers. Datasheet pdf. Equivalent

SN74LV595A-EP Datasheet
Recommendation SN74LV595A-EP Datasheet
Part SN74LV595A-EP
Description 8-Bit Shift Registers
Feature SN74LV595A-EP; D Controlled Baseline − One Assembly/Test Site, One Fabrication Site D Enhanced Diminishing Manufact.
Manufacture etcTI
Datasheet
Download SN74LV595A-EP Datasheet




Texas Instruments SN74LV595A-EP
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree
D 2-V to 5.5-V VCC Operation
D Max tpd of 7.4 ns at 5 V
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
SN74LV595AĆEP
8ĆBIT SHIFT REGISTER
WITH 3ĆSTATE OUTPUT REGISTERS
SCLS568B − JANUARY 2004 − REVISED MAY 2004
D Supports Mixed-Mode Voltage Operation on
All Ports
D 8-Bit Serial-In, Parallel-Out Shift
D Ioff Supports Partial-Power-Down Mode
Operation
D Shift Register Has Direct Clear
PW PACKAGE
(TOP VIEW)
QB
QC
QD
QE
QF
QG
QH
GND
1
2
3
4
5
6
7
8
16 VCC
15 QA
14 SER
13 OE
12 RCLK
11 SRCLK
10 SRCLR
9 QH
description/ordering information
The SN74LV595A is an 8-bit shift register designed for 2-V to 5.5-V VCC operation.
This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The
storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register.
The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output for
cascading. When the output-enable (OE) input is high, all outputs except QHare in the high-impedance state.
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both
clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 85°C
TSSOP − PW Reel of 2000 SN74LV595AIPWREP LV595EP
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2004, Texas Instruments Incorporated
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Texas Instruments SN74LV595A-EP
SN74LV595AĆEP
8ĆBIT SHIFT REGISTER
WITH 3ĆSTATE OUTPUT REGISTERS
SCLS568B − JANUARY 2004 − REVISED MAY 2004
SER
X
X
X
INPUTS
SRCLK SRCLR
XX
XX
XL
RCLK
X
X
X
LH X
HH X
XH X
XX X
XX X
FUNCTION TABLE
FUNCTION
OE
H Outputs QA−QH are disabled.
L Outputs QA−QH are enabled.
X Shift register is cleared.
X
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
X
First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
X Shift-register state is not changed.
X Shift-register data is stored in the storage register.
X Storage-register state is not changed.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265



Texas Instruments SN74LV595A-EP
logic diagram (positive logic)
OE
RCLK
13
12
SRCLR
SRCLK
10
11
SER 14
SN74LV595AĆEP
8ĆBIT SHIFT REGISTER
WITH 3ĆSTATE OUTPUT REGISTERS
SCLS568B − JANUARY 2004 − REVISED MAY 2004
1D Q
C1
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
3D
C3 Q
3D
C3 Q
3D
C3 Q
3D
C3 Q
3D
C3 Q
3D
C3 Q
3D
C3 Q
3D
C3 Q
15
QA
1
QB
2
QC
3
QD
4
QE
5
QF
6
QG
7
QH
9 QH
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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