Positive-NOR Buffers. SN74ALS33A Datasheet

SN74ALS33A Buffers. Datasheet pdf. Equivalent

SN74ALS33A Datasheet
Recommendation SN74ALS33A Datasheet
Part SN74ALS33A
Description Quadruple 2-Input Positive-NOR Buffers
Feature SN74ALS33A; SN54ALS33A, SN74ALS33A QUADRUPLE 2ĆINPUT POSITIVEĆNOR BUFFERS WITH OPENĆCOLLECTOR OUTPUTS SDAS034C −.
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Texas Instruments SN74ALS33A
SN54ALS33A, SN74ALS33A
QUADRUPLE 2ĆINPUT POSITIVEĆNOR BUFFERS
WITH OPENĆCOLLECTOR OUTPUTS
SDAS034C − APRIL 1982 − REVISED FEBRUARY 2009
D Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These devices contain four independent 2-input
positive-NOR buffers with open-collector outputs.
Open-collector outputs require resistive pullup to
perform correctly. They can deliver higher VOH
levels and commonly are used in wired-AND
applications. These devices perform the Boolean
functions Y = A B or Y = A + B in positive logic.
The SN54ALS33A is characterized for operation
over the full military temperature range of − 55°C
to 125°C. The SN74ALS33A is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE
(each gate)
INPUTS
AB
OUTPUT
Y
HX
L
XH
L
LL
H
SN54ALS33A . . . J PACKAGE
SN74ALS33A . . . D OR N PACKAGE
(TOP VIEW)
1Y
1A
1B
2Y
2A
2B
GND
1
2
3
4
5
6
7
14 VCC
13 4Y
12 4B
11 4A
10 3Y
9 3B
8 3A
SN54ALS33A . . . FK PACKAGE
(TOP VIEW)
1B
3 2 1 20 19
4 18
4B
NC 5
17 NC
2Y 6
16 4A
NC 7
15 NC
2A 8
14 3Y
9 10 11 12 13
NC − No internal connection
logic symbol
logic diagram (positive logic)
2
1A
3
1B
5
2A
6
2B
8
3A
9
3B
11
4A
12
4B
1
1
1Y
4
2Y
10
3Y
13
4Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
2
1A
3
1B
5
2A
6
2B
8
3A
9
3B
11
4A
12
4B
1
1Y
4
2Y
10
3Y
13
4Y
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2009, Texas Instruments Incorporated
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Texas Instruments SN74ALS33A
SN54ALS33A, SN74ALS33A
QUADRUPLE 2ĆINPUT POSITIVEĆNOR BUFFERS
WITH OPENĆCOLLECTOR OUTPUTS
SDAS034C − APRIL 1982 − REVISED FEBRUARY 2009
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range, TA: SN54ALS33A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
SN74ALS33A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
VCC
VIH
VIL
VOH
IOL
TA
Supply voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output current
Operating free-air temperature
SN54ALS33A
MIN NOM MAX
4.5 5 5.5
2
0.7
5.5
12
−55 125
SN74ALS33A
MIN NOM MAX
4.5 5 5.5
2
0.8
5.5
24
0 70
UNIT
V
V
V
V
mA
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK VCC = 4.5 V,
VOL
VCC = 4.5 V
II VCC = 5.5 V,
IIH VCC = 5.5 V,
IIL VCC = 5.5 V,
IOH VCC = 4.5 V,
ICCH
VCC = 5.5 V,
ICCL
VCC = 5.5 V,
‡ All typical values are at VCC = 5 V, TA = 25°C.
II = −18 mA
IOL = 12 mA
IOL = 24 mA
VI = 7 V
VI = 2.7 V
VI = 0.4 V
VOH = 5.5 V
VI = 0
VI = 4.5 V
SN54ALS33A
MIN TYP‡ MAX
−1.5
0.25 0.4
0.1
20
− 0.1
0.1
1.7 2.8
5.6 9
SN74ALS33A
MIN TYP‡ MAX
−1.5
0.25 0.4
0.35 0.5
0.1
20
− 0.1
0.1
1.7 2.8
5.6 9
UNIT
V
V
mA
µA
mA
mA
mA
mA
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 680 ,
TA = MIN to MAX§
SN54ALS33A SN74ALS33A
MIN MAX MIN MAX
tPLH
tPHL
A or B
10 59 10
Y
2 18
2
§ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
33
12
UNIT
ns
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265



Texas Instruments SN74ALS33A
From Output
Under Test
CL
(see Note A)
SN54ALS33A, SN74ALS33A
QUADRUPLE 2ĆINPUT POSITIVEĆNOR BUFFERS
WITH OPENĆCOLLECTOR OUTPUTS
SDAS034C − APRIL 1982 − REVISED FEBRUARY 2009
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
VCC
Test
Point
RL
From Output
Under Test
CL
(see Note A)
RL
Test
Point
From Output
Under Test
CL
(see Note A)
7V
RL = R1 = R2
S1
R1
Test
Point
R2
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
Timing
Input
Data
Input
tsu
1.3 V
th
1.3 V
1.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3.5 V
0.3 V
3.5 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
1.3 V
tw
1.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
3.5 V
0.3 V
Output
Control
(low-level
enabling)
tPZL
Waveform 1
S1 Closed
(see Note B)
tPZH
Waveform 2
S1 Open
(see Note B)
1.3 V
1.3 V
tPHZ
1.3 V
1.3 V
tPLZ
3.5 V
0.3 V
[3.5 V
VOL
0.3 V
VOH
0.3 V
[0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
Input
tPLH
In-Phase
Output
tPHL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
1.3 V
1.3 V
3.5 V
0.3 V
tPHL
VOH
1.3 V
VOL
tPLH
VOH
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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