D-TYPE LATCHES. SN54AS373 Datasheet

SN54AS373 LATCHES. Datasheet pdf. Equivalent

SN54AS373 Datasheet
Recommendation SN54AS373 Datasheet
Part SN54AS373
Description OCTAL TRANSPARENT D-TYPE LATCHES
Feature SN54AS373; SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS.
Manufacture etcTI
Datasheet
Download SN54AS373 Datasheet




Texas Instruments SN54AS373
SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS083C – APRIL 1982 – REVISED MARCH 2002
D Eight Latches in a Single Package
D 3-State Bus-Driving True Outputs
D Full Parallel Access for Loading
D Buffered Control Inputs
D pnp Inputs Reduce dc Loading on Data
Lines
description
These octal transparent D-type latches feature
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads. They are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
SN54ALS373A, . . . J OR W PACKAGE
SN54AS373 . . . J PACKAGE
SN74ALS373A, SN74AS373 . . . DW, N, OR NS PACKAGE
(TOP VIEW)
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 LE
While the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
SN54ALS373A, SN54AS373 . . . FK PACKAGE
(TOP VIEW)
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low) or a high-impedance state. In
the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and the increased drive
provide the capability to drive bus lines without
interface or pullup components.
2D
3 2 1 20 19
4 18
8D
2Q 5
17 7D
3Q 6
16 7Q
3D 7
15 6Q
4D 8
14 6D
9 10 11 12 13
OE does not affect internal operations of the
latches. Old data can be retained or new data can
be entered while the outputs are off.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1



Texas Instruments SN54AS373
SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS083C APRIL 1982 REVISED MARCH 2002
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP N
Tube
SN74ALS373AN
SN74AS373N
SN74ALS373AN
SN74AS373N
0°C to 70°C
SOIC DW
Tube
Tape and reel
Tube
Tape and reel
SN74ALS373ADW
SN74ALS373ADWR
SN74AS373DW
SN74AS373DWR
ALS373A
AS373
SOP NS
Tape and reel
SN74ALS373ANSR
SN74AS373NSR
ALS373A
74AS373
CDIP J
Tube
SNJ54ALS373AJ
SNJ54AS373J
SNJ54ALS373AJ
SNJ54AS373J
55°C to 125°C CFP W
Tube
SNJ54ALS373AW
SNJ54ALS373AW
LCCC FK Tube
SNJ54ALS373AFK
SNJ54AS373FK
SNJ54ALS373AFK
SNJ54AS373FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each latch)
INPUTS
OE LE
D
OUTPUT
Q
L HH
H
LHL
L
LLX
HXX
Q0
Z
logic diagram (positive logic)
OE 1
LE 11
3
1D
C1
1D
2 1Q
To Seven Other Channels
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265



Texas Instruments SN54AS373
SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS083C APRIL 1982 REVISED MARCH 2002
absolute maximum ratings over operating free-air temperature range (SN54ALS373A,
SN74ALS373A) (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to any output in the high state or power-off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance, θJA (see Note 1): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
VCC
VIH
VIL
IOH
IOL
TA
Supply voltage
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
SN54ALS373A
MIN NOM MAX
4.5 5 5.5
2
0.7
1
12
55 125
SN74ALS373A
MIN NOM MAX
4.5 5 5.5
2
0.8
2.6
24
0 70
UNIT
V
V
V
mA
mA
°C
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
fclock
tw
tsu
th
Clock frequency
Pulse duration, LE high
Setup time, data before LE
Hold time, data after LE
SN54ALS373A SN74ALS373A
MIN MAX MIN MAX
12 10
10 10
77
UNIT
MHz
ns
ns
ns
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)