EDGE-TRIGGERED FLIP-FLOPS. SN74ALS374A Datasheet

SN74ALS374A FLIP-FLOPS. Datasheet pdf. Equivalent

SN74ALS374A Datasheet
Recommendation SN74ALS374A Datasheet
Part SN74ALS374A
Description OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
Feature SN74ALS374A; SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE O.
Manufacture etcTI
Datasheet
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Texas Instruments SN74ALS374A
SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999
D D-Type Flip-Flops in a Single Package With
3-State Bus Driving True Outputs
D Full Parallel Access for Loading
D Buffered Control Inputs
D Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) DIPs
description
These octal D-type edge-triggered flip-flops
feature 3-state outputs designed specifically for
driving highly capacitive or relatively
low-impedance loads. They are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
SN54ALS374A, SN54AS374 . . . J PACKAGE
SN74ALS374A, SN74AS374 . . . DW OR N PACKAGE
(TOP VIEW)
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 CLK
SN54ALS374A, SN54AS374 . . . FK PACKAGE
(TOP VIEW)
On the positive transition of the clock (CLK) input,
the Q outputs are set to the logic levels set up at
the data (D) inputs.
A buffered output-enable (OE) input places the
eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In
the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and the increased drive
provide the capability to drive bus lines without
interface or pullup components.
3 2 1 20 19
2D 4
18 8D
2Q 5
17 7D
3Q 6
16 7Q
3D 7
15 6Q
4D 8
14 6D
9 10 11 12 13
OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54ALS374A and SN54AS374 are characterized for operation over the full military temperature range
of –55°C to 125°C. The SN74ALS374A and SN74AS374 are characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OE CLK D
OUTPUT
Q
LH
H
LL
L
L H or L X
HXX
Q0
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1



Texas Instruments SN74ALS374A
SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999
logic symbol
logic diagram (positive logic)
OE
CLK
1
11
3
1D
4
2D
7
3D
8
4D
13
5D
14
6D
17
7D
18
8D
EN
C1
1D
2
1Q
5
2Q
6
3Q
9
4Q
12
5Q
15
6Q
16
7Q
19
8Q
OE 1
11
CLK
3
1D
C1
1D
2 1Q
To Seven Other Channels
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Package thermal impedance, θJA (see Note 1): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
VCC
VIH
VIL
IOH
IOL
TA
Supply voltage
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
SN54ALS374A
MIN NOM MAX
4.5 5 5.5
2
0.7
–1
12
–55 125
SN74ALS374A
MIN NOM MAX
4.5 5 5.5
2
0.8
–2.6
24
0 70
UNIT
V
V
V
mA
mA
°C
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265



Texas Instruments SN74ALS374A
SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ALS374A
MIN TYP† MAX
SN74ALS374A
MIN TYP† MAX UNIT
VIK
VOH
VOL
IOZH
IOZL
II
IIH
IIL
IO‡
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
VCC = 4.5 V
VCC = 4.5 V
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
II = –18 mA
IOH = –0.4 mA
IOH = –1 mA
IOH = –2.6 mA
IOL = 12 mA
IOL = 24 mA
VO = 2.7 V
VO = 0.4 V
VI = 7 V
VI = 2.7 V
VI = 0.4 V
VO = 2.25 V
Outputs high
VCC–2
2.4
–20
–1.5
VCC–2
3.3
2.4
0.25 0.4
20
–20
0.1
20
–0.2
–112
11 20
–30
–1.5
3.2
0.25 0.4
0.35 0.5
20
–20
0.1
20
–0.2
–112
11 19
V
V
V
µA
µA
mA
µA
mA
mA
ICC
VCC = 5.5 V
Outputs low
19 28
19 28 mA
Outputs disabled
20 31
20 31
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
fclock
tw
tsu
th
Clock frequency
Pulse duration
Setup time
Hold time
CLK high or low
Data before CLK
Data after CLK
SN54ALS374A
MIN MAX
30
16.5
10
4
SN74ALS374A
MIN MAX
35
14
10
0
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating conditions (unless otherwise noted
(see Figure 3)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
CLK
OE
OE
TO
(OUTPUT)
Q
Q
Q
SN54ALS374A
MIN MAX
30
3 14
5 17
3 18
5 21
1 11
2 19
SN74ALS374A
MIN MAX
35
3 12
5 16
3 17
5 18
1 10
2 18
UNIT
MHz
ns
ns
ns
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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