32-bit MCU. SPC56AP54L3 Datasheet

SPC56AP54L3 MCU. Datasheet pdf. Equivalent

SPC56AP54L3 Datasheet
Recommendation SPC56AP54L3 Datasheet
Part SPC56AP54L3
Description 32-bit MCU
Feature SPC56AP54L3; SPC56AP60x, SPC56AP54x SPC560P60x, SPC560P54x 32-bit Power Architecture® based MCU with 1088KB Flash.
Manufacture STMicroelectronics
Datasheet
Download SPC56AP54L3 Datasheet




STMicroelectronics SPC56AP54L3
SPC56AP60x, SPC56AP54x
SPC560P60x, SPC560P54x
32-bit Power Architecture® based MCU with 1088KB Flash memory
and 80KB RAM for automotive chassis and safety applications
Datasheet - production data
LQFP100
14 x 14 mm
LQFP144
20 x 20 mm
Features
AEC-Q10x qualified
64 MHz, single issue, 32-bit CPU core complex
(e200z0h)
– Compliant with Power Architecture®
embedded category
– Variable Length Encoding (VLE)
Memory organization
– Up to 1024 KB on-chip code Flash memory
with additional 64 KB for EEPROM
emulation (data flash), with ECC, with
erase/program controller
– Up to 80 KB on-chip SRAM with ECC
Fail safe protection
– ECC protection on system SRAM and
Flash
– Safety port
– SWT with servicing sequence pseudo-
random generator
– Power management
– Non-maskable interrupt for both cores
– Fault collection and control unit (FCCU)
– Safe mode of system-on-chip (SoC)
– Register protection scheme
Nexus® L2+ interface
Single 3.3 V or 5 V supply for I/Os and ADC
2 on-platform peripherals set with 2 INTC
16-channel eDMA controller with multiple
transfer request sources
General purpose I/Os (80 GPIO + 26 GPI on
LQFP144; 49 GPIO + 16 GPI on LQFP100)
2 general purpose eTimer units
– 6 timers, each with up/down count
capabilities
– 16-bit resolution, cascadable counters
– Quadrature decode with rotation direction
flag
– Double buffer input capture and output
compare
Communications interfaces
– 2 LINFlex modules (LIN 2.1,
1 × Master/Slave, 1 × Master Only)
– 5 DSPI modules with automatic chip select
generation
– 2 FlexCAN interfaces (2.0B Active) with 32
message buffers
– 1 Safety port based on FlexCAN; usable as
third CAN when not used as safety port
– 1 FlexRay™ module (V2.1) with dual or
single channel, 64 message buffers and up
to 10 Mbit/s
2 CRC units with three contexts and 3
hardwired polynomials(CRC8,CRC32 and
CRC-16-CCITT)
10-bit A/D converter
– 27 input channels and pre-sampling feature
– Conversion time < 1 µs including sampling
time at full precision
– Programmable cross triggering unit (CTU)
– 4 analog watchdog with interrupt capability
On-chip CAN/UART Bootstrap loader with boot
assist module (BAM)
Ambient temperature ranges: –40 to 125 °C or
–40 to 105 °C
June 2016
This is information on a product in full production.
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STMicroelectronics SPC56AP54L3
Package
LQFP144
LQFP100
SPC56xP54x, SPC56xP60x
Table 1. Device summary
Part number
768 KB Flash
SPC560P54L5
SPC56AP54L5
SPC560P54L3
SPC56AP54L3
1 MB Flash
SPC560P60L5
SPC56AP60L5
SPC560P60L3
SPC56AP60L3
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DocID18340 Rev 6



STMicroelectronics SPC56AP54L3
SPC56xP54x, SPC56xP60x
Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.1 High performance e200z0h core processor . . . . . . . . . . . . . . . . . . . . . . 14
1.5.2 Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.3 Enhanced direct memory access (eDMA) . . . . . . . . . . . . . . . . . . . . . . . 15
1.5.4 On-chip flash memory with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5.5 On-chip SRAM with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5.6 Interrupt controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5.7 System clocks and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.8 Frequency modulated phase-locked loop (FMPLL) . . . . . . . . . . . . . . . . 17
1.5.9 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.10 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.11 Periodic interrupt timer (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.12 System timer module (STM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.13 Software watchdog timer (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.14 Fault collection and control unit (FCCU) . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.15 System integration unit (SIUL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.16 Boot and censorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.17 Error correction status module (ECSM) . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.18 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.19 Safety port (FlexCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5.20 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5.21 Serial communication interface module (LINFlex) . . . . . . . . . . . . . . . . . 22
1.5.22 Deserial serial peripheral interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . 22
1.5.23 eTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5.24 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.5.25 Cross triggering unit (CTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.5.26 Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.5.27 Nexus development interface (NDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.5.28 IEEE 1149.1 (JTAG) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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