MIXED-SIGNAL MICROCONTROLLER. MSP430L092 Datasheet

MSP430L092 MICROCONTROLLER. Datasheet pdf. Equivalent

Part MSP430L092
Description MIXED-SIGNAL MICROCONTROLLER
Feature MSP430L092 MSP430C09x www.ti.com MIXED SIGNAL MICROCONTROLLER SLAS673 – SEPTEMBER 2010 FEATURES .
Manufacture etcTI
Datasheet
Download MSP430L092 Datasheet



MSP430L092
MSP430L092
MSP430C09x
www.ti.com
MIXED SIGNAL MICROCONTROLLER
SLAS673 – SEPTEMBER 2010
FEATURES
1
• Ultra-Low Supply Voltage (ULV) Range
– 0.9 V to 1.5 V (1 MHz)
– 1.5 V to 1.65 V (4 MHz)
• Low Power Consumption
– Active Mode (AM): 45 µA/MHz (1.3 V)
– Standby Mode (LPM3, WDT_A Mode): 6 µA
– Off Mode (LPM4): 3 µA
• Wake-Up From LPMx in Less Than 5 µs
• 16-Bit RISC Architecture
– Extended Instructions
– Up to 4-MHz System Clock
• Compact Clock System
– 1-MHz Internal Trimmable High-Frequency
Clock
– 20-kHz Internal Low-Frequency Clock
Source
– External Clock Input
• 16-Bit Timer0_A3 With Three Capture/Compare
Registers
• 16-Bit Timer1_A3 With Three Capture/Compare
Registers
• ULV Analog Pool Modes
– 8-Bit Analog-to-Digital Converter (ADC)
– 8-Bit Digital-to-Analog Converter (DAC)
– Programmable Comparator (COMP)
– Supply Voltage Monitor (SVM)
– Temperature Sensor
– Internal Reference Voltage Source
• ULV Port Logic
– VOL Better Than 0.15 V at 2.5 mA
– VOH Better Than VCC – 0.15 V at 1 mA
– Timer0 PWM Signal Available on All Ports
– Timer1 PWM Signal Available on All Ports
• ULV Brownout Circuit (BOR)
• ULV RAM Retention Voltage Below BOR Level
• 32-Bit Watchdog Timer (WDT-A)
• Bootstrap Loader in MSP430L092
Development/Prototyping Device
• Full Four-Wire JTAG Debug Interface
• Family Members Include
– MSP430C091
– 1KB ROM Memory
– 128 Bytes RAM + 96 Bytes CRAM
(Lockable)
– MSP430C092
– 2KB ROM Memory
– 128 Bytes RAM + 96 Bytes CRAM
(Lockable)
– MSP430L092
– 2KB Loader ROM With Service
Functions
– 2KB RAM
(1792 + 128 + 96 Bytes Lockable)
• For Complete Module Descriptions, See the
MSP430x09x Family User’s Guide (SLAU321)
DESCRIPTION
The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled internal oscillators allow wake-up from low-power modes to active mode in less than 5 µs.
The MSP430C09x and MSP430L092 series are microcontroller configurations with two 16-bit timers, an
ultra-low-voltage 8-bit analog-to-digital (A/D) converter, an 8-bit digital-to-analog (D/A) converter, and up to 11 I/O
pins.
Typical applications for this device include single-cell systems requiring a full analog signal chain.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated



MSP430L092
MSP430L092
MSP430C09x
SLAS673 – SEPTEMBER 2010
ORDERING INFORMATION(1)
TA
PACKAGED DEVICES(2)
PLASTIC 14-PIN TSSOP (PW)
MSP430C091SPW
0ºC to 50ºC
MSP430C092SPW
MSP430L092SPW
(1) For the most current package and ordering information, see the
Package Option Addendum at the end of this document, or see the
TI web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data,
symbolization, and PCB design guidelines are available at
www.ti.com/package.
Pin Designation, MSP430C091PW, MSP430C092PW
www.ti.com
TCK/P2.0/TA 0.2/TA1.2/TA1.1
TMS/P2.1/TA 0.2/TA1.2/TA0.1
TDI/P2.2/TA0.2/TA1.2/CxOUT/CCI0.0
TDO/P2.3/TA0.2/TA 1.2/CCI1.0
RST/NMI/SVMOUT
P1.0/TA0.2/TA1.2/ACLK/CCI0.1/A2/CLKIN
P1.1/TA0.2/TA1.2/SMCLK/CCI1.1/A1/TA0CLK
PW PACKAGE
(TOP VIEW)
1 14
2 13
3 12
4 11
5 10
69
78
P1.6/TA0.2/TA1.2/TA 1.1
P1.5/TA0.2/TA1.2/TA 0.1
P1.4/TA0.2/TA1.2/MCLK/A0/TA1CLK
VCC
VSS/GND
P1.3/TA0.2/TA1.2/CxOUT/CCI1.0/VREF/A3
P1.2/TA0.2/TA1.2/ACLK/CCI0.0/AOUT/A3
Functional Block Diagram, MSP430C092PW, MSP430C091PW
RST/NMI/SVMOUT VCC
GND/VSS
P1.0...P1.6
P2.0...P2.3
CLKIN
LF-OSC
HF-OSC
Clock
System
ACLK
SMCLK
MCLK
Reset
Int-Logic
2/(1)KB ROM
128B RAM
+96B CRAM
I/O Port P1L
7 I/Os with
Interrupt
Capability
I/O Port P2L
4 I/Os with
Interrupt
Capability
CPU &
Working
Registers
TMS, TCK,
TDI, TDO
VREF
4W-JTAG
Debug
support
CORE
ULV
Brownout
Watchdog
WDTA
32/16-Bit
Timer0_A3
3 CC
Registers
Timer1_A3
3 CC
Register
Analog-
Pool
ULV -Ref.,
8-Bit ADC,
8-Bit DAC,
Comparator,
SVS
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Copyright © 2010, Texas Instruments Incorporated





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