Synchronous SRAM. IDT71V546S Datasheet

IDT71V546S SRAM. Datasheet pdf. Equivalent

IDT71V546S Datasheet
Recommendation IDT71V546S Datasheet
Part IDT71V546S
Description Synchronous SRAM
Feature IDT71V546S; 128K x 36, 3.3V Synchronous IDT71V546S SRAM with ZBT™ Feature Burst Counter and Pipelined Outputs.
Manufacture Renesas
Datasheet
Download IDT71V546S Datasheet




Renesas IDT71V546S
128K x 36, 3.3V Synchronous
IDT71V546S
SRAM with ZBTFeature
Burst Counter and Pipelined Outputs
Features
128K x 36 memory configuration, pipelined outputs
Supports high performance system speed - 133 MHz
(4.2 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read
cycles
Internally synchronized registered outputs eliminate the
need to control OE
Single R/W (READ/WRITE) control pin
Functional Block Diagram
LBO
Address A [0:16]
CE1, CE2, CE2
R/W
CEN
ADV/LD
BWx
DQ
DQ
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
Single 3.3V power supply (±5%)
Packaged in a JEDEC standard 100-pin TQFP package
Green parts available, see Ordering Information
128K x 36 BIT
MEMORY ARRAY
Address
Control
DI DO
DQ
Clk
Control Logic
Clock
Mux
Sel
D
Output Register
Q
OE Gate
.3821 drw 01
Data I/O [0:31], I/O P[1:4]
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
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©2017 Integrated Device Technology, Inc.
AUGUST 2017
DSC-3821/07



Renesas IDT71V546S
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBTFeature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Description
The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM organized as 128K x 36 bits. It is designed to
eliminate dead bus cycles when turning the bus around between reads
and writes, or writes and reads. Thus it has been given the name ZBTTM,
or Zero Bus Turn-around.
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later its associated data cycle occurs, be it
read or write.
The IDT71V546 contains data I/O, address and control signal regis-
ters. Output enable is the only asynchronous signal and can be used to
disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V546 to be
suspended as long as necessary. All synchronous inputs are ignored
whenCEN ishighandtheinternaldeviceregisterswillholdtheirprevious
values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
todeselectthedevicewhendesired. Ifanyoneofthesethreeisnotactive
when ADV/LDis low, no new memory operation can be initiated and any
burst that was in progress is stopped. However, any pending data
transfers(readsorwrites)willbecompleted. Thedatabuswilltri-statetwo
cycles after the chip is deselected or a write initiated.
The IDT71V546 has an on-chip burst counter. In the burst mode, the
IDT71V546 can provide four cycles of data for a single address presented
totheSRAM. TheorderoftheburstsequenceisdefinedbytheLBOinput
pin. The LBOpinselectsbetweenlinearandinterleavedburstsequence.
The ADV/LD signal is used to load a new external address (ADV/LD =
LOW) or increment the internal burst counter (ADV/LD = HIGH).
The IDT71V546 SRAM utilizes a high-performance, high-volume
3.3V CMOS process, and is packaged in a JEDEC standard 14mm x
20mm 100- pin thin plastic quad flatpack (TQFP) for high board density.
Pin Description Summary
A0 - A16
Address Inputs
CE1, CE2, CE2
Three Chip Enables
OE Output Enable
R/W Read/Write Signal
CEN Clock Enable
BW1, BW2, BW3, BW4 Individual Byte Write Selects
CLK Clock
ADV/LD
Advance Burst Address / Load New Address
LBO Linear / Interleaved Burst Order
I/O0 - I/O31, I/OP1 - I/OP4 Data Input/Output
VDD 3.3V Power
VSS Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Static
Static
3821 tbl 01
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Renesas IDT71V546S
IDT71V546 128K x 36, 3.3V Synchronous SRAM with
ZBTFeature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O Active
Description
A0 - A16
Address Inputs
I N/A Synchronous Address inputs. The address register is triggered by a
combination of the rising edge of CLK and ADV/LD Low, CEN Low and true
chip enables.
ADV/LD
Address/Load
I N/A ADV/LD is a synchronous input that is used to load the internal registers with
new address and control when it is sampled low at the rising edge of clock with
the chip selected. When ADV/LD is low with the chip deselected, any burst in
progress is terminated. When ADV/LD is sampled high then the internal burst
counter is advanced for any burst that was in progress. The external addresses
are ignored when ADV/LD is sampled high.
R/W Read/Write I N/A R/W signal is a synchronous input that identified whether the current load cycle
initiated is a Read or Write access to the memory array. The data bus activity for
the current cycle takes place two clock cycles later.
CEN Clock Enable I LOW Synchrono us Clock Enable Input. When CEN is sampled high, all other
synchronous inputs, includ ing clock are ignored and outputs remain unchanged.
The effect of CEN samp led high on the device outputs is as if the low to high
clock transition did not occur. For normal operation, CEN must be sampled low
at rising edge of clock.
BW1 - BW4
Individual Byte
Write Enables
I LOW Synchronous byte write enables. Enable 9-bit byte has its own active low byte
write enable. On load write cycles (When R/W and ADV/LD are sampled low)
the appropriate byte write signal (BW1 - BW4) must be valid. The byte write
signal must also be valid on each cycle of a burst write. Byte Write signals are
ignored when R/W is sampled high. The appropriate byte(s) of data are written
into the device two cycles later. BW1 - BW4 can all be tied low if always doing
write to the entire 36-bit word.
CE1, CE2
Chip Enables
I LOW Synchro nous active low chip enable. CE1 and CE2 are used with CE2 to
enable the IDT71V546. (CE1 or CE2 sampled high or CE2 sampled low) and
ADV/LD low at the rising edge of clock, initiates a deselect cycle. the ZBT
has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after
deselect is initiated.
CE2 Chip Enable I HIGH Synchronout active high chip enable. CE2 is used with CE1 and CE2 to enable
the chip. CE2 has inverted polarity but otherwise identical to CE1 and CE2.
CLK Clock I N/A This is the clock input to the IDT71V546. Except for OE, all timing references for
the device are made with respect to the rising edge of CLK.
I/O0 - I/O31
I/OP1 - I/OP4
Data Input/Output
I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data
output path are registered and triggered by the rising edge of CLK.
LBO Linear Burst I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is
Order
selected. When LBO is low the Linear burst sequence is selected. LBO is a
static DC input.
OE Output Enable I LOW Asynchronous output enable. OE must be low to read data from the 71V546.
When OE is high the I/O pins are in a high-impedance state. OE does not need
to be actively controlled for read and write cycles. In normal operation, OE can
be tied low.
VDD
Power Supply
N/A N/A 3.3V power supply input.
VSS
Ground
N/A N/A Ground pin.
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
3821 tbl 02
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