Synchronous SRAM. IDT71V546S Datasheet

IDT71V546S SRAM. Datasheet pdf. Equivalent

Part IDT71V546S
Description Synchronous SRAM
Feature 128K x 36, 3.3V Synchronous IDT71V546S SRAM with ZBT™ Feature Burst Counter and Pipelined Outputs.
Manufacture Renesas
Datasheet
Download IDT71V546S Datasheet



IDT71V546S
128K x 36, 3.3V Synchronous
IDT71V546S
SRAM with ZBTFeature
Burst Counter and Pipelined Outputs
Features
128K x 36 memory configuration, pipelined outputs
Supports high performance system speed - 133 MHz
(4.2 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read
cycles
Internally synchronized registered outputs eliminate the
need to control OE
Single R/W (READ/WRITE) control pin
Functional Block Diagram
LBO
Address A [0:16]
CE1, CE2, CE2
R/W
CEN
ADV/LD
BWx
DQ
DQ
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
Single 3.3V power supply (±5%)
Packaged in a JEDEC standard 100-pin TQFP package
Green parts available, see Ordering Information
128K x 36 BIT
MEMORY ARRAY
Address
Control
DI DO
DQ
Clk
Control Logic
Clock
Mux
Sel
D
Output Register
Q
OE Gate
.3821 drw 01
Data I/O [0:31], I/O P[1:4]
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
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©2017 Integrated Device Technology, Inc.
AUGUST 2017
DSC-3821/07



IDT71V546S
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBTFeature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Description
The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM organized as 128K x 36 bits. It is designed to
eliminate dead bus cycles when turning the bus around between reads
and writes, or writes and reads. Thus it has been given the name ZBTTM,
or Zero Bus Turn-around.
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later its associated data cycle occurs, be it
read or write.
The IDT71V546 contains data I/O, address and control signal regis-
ters. Output enable is the only asynchronous signal and can be used to
disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V546 to be
suspended as long as necessary. All synchronous inputs are ignored
whenCEN ishighandtheinternaldeviceregisterswillholdtheirprevious
values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
todeselectthedevicewhendesired. Ifanyoneofthesethreeisnotactive
when ADV/LDis low, no new memory operation can be initiated and any
burst that was in progress is stopped. However, any pending data
transfers(readsorwrites)willbecompleted. Thedatabuswilltri-statetwo
cycles after the chip is deselected or a write initiated.
The IDT71V546 has an on-chip burst counter. In the burst mode, the
IDT71V546 can provide four cycles of data for a single address presented
totheSRAM. TheorderoftheburstsequenceisdefinedbytheLBOinput
pin. The LBOpinselectsbetweenlinearandinterleavedburstsequence.
The ADV/LD signal is used to load a new external address (ADV/LD =
LOW) or increment the internal burst counter (ADV/LD = HIGH).
The IDT71V546 SRAM utilizes a high-performance, high-volume
3.3V CMOS process, and is packaged in a JEDEC standard 14mm x
20mm 100- pin thin plastic quad flatpack (TQFP) for high board density.
Pin Description Summary
A0 - A16
Address Inputs
CE1, CE2, CE2
Three Chip Enables
OE Output Enable
R/W Read/Write Signal
CEN Clock Enable
BW1, BW2, BW3, BW4 Individual Byte Write Selects
CLK Clock
ADV/LD
Advance Burst Address / Load New Address
LBO Linear / Interleaved Burst Order
I/O0 - I/O31, I/OP1 - I/OP4 Data Input/Output
VDD 3.3V Power
VSS Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Static
Static
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