CLOCK MULTIPLIER. ICS601-01 Datasheet

ICS601-01 MULTIPLIER. Datasheet pdf. Equivalent

Part ICS601-01
Description LOW PHASE NOISE CLOCK MULTIPLIER
Feature LOW PHASE NOISE CLOCK MULTIPLIER DATASHEET ICS601-01 Description The ICS601-01 is a low-cost, low .
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Datasheet
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ICS601-01
LOW PHASE NOISE CLOCK MULTIPLIER
DATASHEET
ICS601-01
Description
The ICS601-01 is a low-cost, low phase noise,
high-performance clock synthesizer for applications
which require low phase noise and low jitter. It is IDT’s
lowest phase noise multiplier, and also the lowest
CMOS part in the industry. Using IDT’s patented
analog and digital Phase-Locked Loop (PLL)
techniques, the chip accepts a 10 - 27 MHz crystal or
clock input, and produces output clocks up to 156 MHz
at 3.3 V.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
For applications which require definted input to output
timing, use the ICS670-01.
Block Diagram
Features
Packaged in 16-pin SOIC or TSSOP
Pb (lead) free package
Uses fundamental 10 - 27 MHz crystal or clock
Patented PLL with the lowest phase noise
Output clocks up to 156 MHz at 3.3 V
Low phase noise: -132 dBc/Hz at 10 kHz
Low jitter - 18 ps one sigma typ.
Full swing CMOS outputs with 25 mA drive capability
at TTL levels
Advanced, low power, sub-micron CMOS process
Industrial temperature range available
Operating voltage of 3.3V or 5V
X1/ICLK
Crystal or
clock input
X2
Reference
Divider
Crystal
Oscillator
Phase
Comparator
VDD
3
Charge
Pump
Loop
Filter
VCO
CLK
ROM Based
Multipliers
VCO
Divide
4
S3:0
3
GND
REFOUT
OE REFEN
IDT™ / ICS™ LOW PHASE NOISE CLOCK MULTIPLIER
1
ICS601-01 REV N 051310



ICS601-01
ICS601-01
LOW PHASE NOISE CLOCK MULTIPLIER
CLOCK MULTIPLIER
Pin Assignment
CLK
REFEN
VDD
VDD
VDD
X2
S1
X1/ICLK
1
2
3
4
5
6
7
8
16 GND
15 GND
14 GND
13 REFOUT
12 OE
11 S0
10 S3
9 S2
16 Pin (150 mil) TSSOP or SOIC
Pin Descriptions
Multiplier Select Table
S3 S2 S1 S0 CLK (see note 2 on following page)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TEST
TEST
Input x1
Input x3
Input x4
Input x5
Input x6
Input x8
TEST
Crystal osc. pass through (no PLL)
Input x2
TEST
Input x8
Input x10
Input x12
Input x16
0 = connect directly to ground
1 = connect directly to VDD
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14 - 16
Pin
Name
CLK
REFEN
VDD
VDD
VDD
X2
S1
X1/ICLK
S2
S3
S0
OE
REFOUT
GND
Pin
Type
Output
Input
Power
Power
Power
XO
Input
XI
Input
Input
Input
Input
Output
Power
Pin Description
Clock output from VCO. Output frequency equals the input frequency times multiplier.
Reference clock enable. Turns off the buffered crystal oscillator clock (stops low) when low.
Connect to +3.3V or +5V. Must match other VDDs.
Connect to +3.3V or +5V. Must match other VDDs.
Connect to +3.3V or +5V. Must match other VDDs.
Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal.
Leave disconnected for an external clock input.
Multiplier select pin 1. Determines CLK output per table above. Internal pull-up.
Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal or clock.
Multiplier select pin 2. Determines CLK output per table above. Internal pull-up.
Multiplier select pin 3. Determines CLK output per table above. Internal pull-up.
Multiplier select pin 0. Determines CLK output per table above. Internal pull-up.
Output Enable. Tri-states both output clocks when low. Internal pull-up.
Buffered crystal oscillator clock output. Controlled by REFIN.
Connect to ground.
IDT™ / ICS™ LOW PHASE NOISE CLOCK MULTIPLIER
2
ICS601-01 REV N 051310





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