Fanout Buffer. 83026I Datasheet

83026I Buffer. Datasheet pdf. Equivalent

Part 83026I
Description Differential-to-LVCMOS/LVTTL Fanout Buffer
Feature Low Skew, 1-to-2, Differential-to-LVCMOS/LVTTL Fanout 83026I Datasheet General Description The 830.
Manufacture Renesas
Datasheet
Download 83026I Datasheet



83026I
Low Skew, 1-to-2,
Differential-to-LVCMOS/LVTTL Fanout
83026I
Datasheet
General Description
The 83026I is a low skew, 1-to-2 Differential-to- LVCMOS/LVTTL
Fanout Buffer and a member of the family of High Performance
Clock Solutions from IDT.The differential input can accept most
differential signal types (LVDS, LVHSTL, LVPECL, SSTL, and HCSL)
and translate to two single-ended LVCMOS/LVTTL outputs with a
maximum output skew of 20ps. The small 8-lead SOIC footprint
makes this device ideal for use in applications with limited board
space.
Features
Two LVCMOS/LVTTL outputs
Differential CLK/nCLK input pair
CLK/nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Output frequency: 350MHz (typical)
Output skew: 20ps (maximum)
Part-to-part skew: 600ps (maximum)
Additive phase jitter, RMS: 0.092ps (typical)
Small 8 lead SOIC package saves board space
Full 3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
CLK Pulldown
nCLK Pullup
Q0
Q1
Pin Assignment
nc
CLK
nCLK
nc
1
2
3
4
8 VDD
7 Q0
6 Q1
5 GND
83026I
8-Lead SOIC, 150Mil
3.9mm x 4.9mm x 1.375mm package body
M Package
Top View
©2015 Integrated Device Technology, Inc
1
December 15, 2015



83026I
83026I Datasheet
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 4 nc Unused
No connect.
2
CLK
Input
Pulldown Non-inverting differential clock input.
3
nCLK
Input
Pullup Inverting differential clock input.
5
GND
Power
Power supply ground.
6 Q1 Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
7 Q0 Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
8 VDD Power
Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN Input Capacitance
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
CPD
Power Dissipation Capacitance
(per output)
ROUT
Output Impedance
Test Conditions
VDD = 3.6V
Minimum
Typical
4
51
51
23
57
Maximum
12
Units
pF
k
k
pF
©2015 Integrated Device Technology, Inc
2
December 15, 2015





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