Differential-to-LVCMOS Translator/Buffer. 83023I Datasheet

83023I Translator/Buffer. Datasheet pdf. Equivalent

Part 83023I
Description Differential-to-LVCMOS Translator/Buffer
Feature Dual, 1-TO-1 Differential-to-LVCMOS Translator/Buffer 83023I Data Sheet GENERAL DESCRIPTION The 83.
Manufacture Renesas
Datasheet
Download 83023I Datasheet



83023I
Dual, 1-TO-1
Differential-to-LVCMOS Translator/Buffer
83023I
Data Sheet
GENERAL DESCRIPTION
The 83023I is a dual, 1-to-1 Differential-to-LVCMOS
Translator/Fanout Buffer.The differential inputs can accept most
differential signal types (LVDS, LVHSTL, LVPECL, SSTL, and
HCSL) and translate into two single-ended LVCMOS outputs.
The small 8-lead SOIC footprint makes this device ideal for use
in applications with limited board space.
Features
Two LVCMOS / LVTTL outputs
Two differential CLKx, nCLKx input pairs
CLK, nCLK pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 350MHz (typical)
Output skew: 60ps (maximum)
Part-to-part skew: 500ps (maximum)
Additive phase jitter, RMS: 0.14ps (typical)
Small 8 lead SOIC package saves board space
3.3V operating supply
-40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
CLK0
nCLK0
CLK1
nCLK1
Q0
Q1
PIN ASSIGNMENT
CLK0
nCLK0
nCLK1
CLK1
1
2
3
4
8 VDD
7 Q0
6 Q1
5 GND
83023I
8-Lead SOIC
3.8mm x 4.8mm x 1.47mm package body
M Package
Top View
©2015 Integrated Device Technology, Inc
1
December 14, 2015



83023I
83023I Data Sheet
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
CLK0
Input Pulldown Non-inverting differential clock input.
2
nCLK0
Input
Pullup Inverting differential clock input.
3
nCLK1
Input
Pullup Inverting differential clock input.
4
CLK1
Input Pulldown Non-inverting differential clock input.
5
GND
Power
Power supply ground.
6 Q1 Output
Single clock output. LVCMOS / LVTTL interface levels.
7 Q0 Output
Single clock output. LVCMOS / LVTTL interface levels.
8 VDD Power
Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
CIN Input Capacitance
CPD
Power Dissipation Capacitance
(per output)
RPULLUP
RPULLDOWN
ROUT
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
VDD = 3.6V
Minimum
Typical
4
23
51
51
7
Maximum Units
pF
pF
kΩ
kΩ
Ω
©2015 Integrated Device Technology, Inc
2
December 14, 2015





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