CMOS SyncFIFO. IDT72V3623 Datasheet

IDT72V3623 SyncFIFO. Datasheet pdf. Equivalent

IDT72V3623 Datasheet
Recommendation IDT72V3623 Datasheet
Part IDT72V3623
Description CMOS SyncFIFO
Feature IDT72V3623; 3.3 VOLT CMOS SyncFIFOTM WITH BUS-MATCHING 256 x 36 IDT72V3623 1,024 x 36 IDT72V3643 LEAD FINI.
Manufacture Renesas
Datasheet
Download IDT72V3623 Datasheet




Renesas IDT72V3623
3.3 VOLT CMOS SyncFIFOTM WITH
BUS-MATCHING
256 x 36
IDT72V3623
1,024 x 36
IDT72V3643
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
FEATURES:
Memory storage capacity:
IDT72V3623–256 x 36
IDT72V3643–1,024 x 36
Clock frequencies up to 100 MHz (6.5 ns access time)
Clocked FIFO buffering data from Port A to Port B
IDT Standard timing (using EF and FF) or First Word Fall
Through Timing (using OR and IR flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
Serial or parallel programming of partial flags
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
Big- or Little-Endian format for word and byte bus sizes
Reset clears data and configures FIFO, Partial Reset clears
data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Easily expandable in width and depth
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Pin and functionally compatible versions of the 5V operating
IDT723623/723643
Industrial temperature range (–40°C to +85°C) is available
Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
MBF1
CLKA
CSA
W/RA
ENA
MBA
RS1
RS2
PRS
Port-A
Control
Logic
FIFO1
Mail1,
Mail2,
Reset
Logic
36
Mail 1
Register
36
RAM ARRAY
36
256 x 36
1,024 x 36
36
A0-A35
Write
Pointer
Read
Pointer
B0-B35
FF/IR
AF
Status Flag
Logic
EF/OR
AE
SPM
FS0/SD
FS1/SEN
36
Programmable Flag
Timing
Offset Registers
Mode
10
MBF2
Mail 2
Register
IDT and the IDT logo are registered trademark of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
© 2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
36
Port-B
Control
Logic
FWFT
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
4662 drw01
MARCH 2018
DSC-4662/8



Renesas IDT72V3623
IDT72V3623/72V3643 CMOS 3.3V SyncBiFIFOTM WITH BUS-MATCHING
256 x 36, 1,024 x 36
COMMERCIAL TEMPERATURERANGE
DESCRIPTION:
The IDT72V3623/72V3643 are pin and functionally compatible
versions of the IDT723623/723643, designed to run off a 3.3V supply for
exceptionally low power consumption. These devices are monolithic,
high-speed, low-power, CMOS unidirectional Synchronous (clocked)
FIFO memory which supports clock frequencies up to 100 MHz and has
read access times as fast as 6.5 ns. The 256/1,024 x 36 dual-port SRAM
FIFO buffers data from Port A to Port B. FIFO data on Port B can output
in 36-bit, 18-bit, or 9-bit formats with a choice of Big- or Little-Endian
configurations.
These devices are synchronous (clocked) FIFOs, meaning each port
employs a synchronous interface. All data transfers through a port are gated
PIN CONFIGURATION
INDEX
W/RA
ENA
CLKA
GND
A35
A34
A33
A32
Vcc
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
BE/FWFT
GND
A22
VCC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
VCC
A12
GND
A11
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
NOTE:
1. NC – no internal connection
TQFP (PK128, order code: PF)
TOP VIEW
2
102 CLKB
101 VCC
100 VCC
99 B35
98 B34
97 B33
96 B32
95 GND
94 GND
93 B31
92 B30
91 B29
90 B28
89 B27
88 B26
87 VCC
86 B25
85 B24
84 BM
83 GND
82 B23
81 B22
80 B21
79 B20
78 B19
77 B18
76 GND
75 B17
74 B16
73 SIZE
72 VCC
71 B15
70 B14
69 B13
68 B12
67 GND
66 B11
65 B10
4662 drw02



Renesas IDT72V3623
IDT72V3623/72V3643 CMOS 3.3V SyncBiFIFOTM WITH BUS-MATCHING
256 x 36, 1,024 x 36
COMMERCIAL TEMPERATURERANGE
to the LOW-to-HIGH transition of a port clock by enable signals. The
clocks for each port are independent of one another and can be
asynchronous or coincident. The enables for each port are arranged to
provide a simple bidirectional interface between microprocessors and/or
buses with synchronous control.
Communication between each port may bypass the FIFO via two
mailbox registers. The mailbox registers' width matches the selected Port
B bus width. Each mailbox register has a flag (MBF1 and MBF2) to signal
when new mail has been stored.
TwokindsofresetareavailableontheseFIFOs: ResetandPartialReset.
Resetinitializesthereadandwritepointerstothefirstlocationofthememoryarray
and selects serial flag programming, parallel flag programming, or one of three
possible default flag offset settings, 8, 16 or 64.
Partial Reset also sets the read and write pointers to the first location of the
memory. Unlike Reset, any settings existing prior to Partial Reset (i.e.,
programmingmethodandpartialflagdefaultoffsets)areretained. PartialReset
is useful since it permits flushing of the FIFO memory without changing any
configuration settings.
These devices have two modes of operation: In the IDT Standard mode,
the first word written to an empty FIFO is deposited into the memory array. A
read operation is required to access that word (along with all other words
residing in memory). In the First Word Fall Through mode (FWFT), the first
word written to an empty FIFO appears automatically on the outputs, no read
operation required (Nevertheless, accessing subsequent words does neces-
sitate a formal read request). The state of the BE/FWFT pin during Reset
determines the mode in use.
The FIFO has a combined Empty/Output Ready Flag (EF/OR ) and a
combinedFull/InputReadyFlag(FF/IR). TheEFandFFfunctionsareselected
in the IDT Standard mode. EF indicates whether or not the FIFO memory is
empty. FF shows whether the memory is full or not. The IR and OR
functions are selected in the First Word Fall Through mode. IR indicates
whether or not the FIFO has available memory locations. OR shows
whether the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
The FIFO has a programmable Almost-Empty flag (AE) and a
programmable Almost-Full flag (AF). AE indicates when a selected
number of words remain in the FIFO memory. AF indicates when the
FIFO contains more than a selected number of words.
FF/IR and AF are two-stage synchronized to the port clock that writes data
into its array. EF/OR and AE are two-stage synchronized to the port clock that
reads data from its array. Programmable offsets for AE and AF are loaded in
parallel using Port A or in serial via the SD input. The Serial Programming Mode
pin (SPM) makes this selection. Three default offset settings are also provided.
The AE threshold can be set at 8, 16 or 64 locations from the empty boundary
and the AF threshold can be set at 8, 16 or 64 locations from the full boundary.
All these choices are made using the FS0 and FS1 inputs during Reset.
Two or more devices may be used in parallel to create wider data paths.
In First Word Fall Through mode, more than one device may be connected in
series to create greater word depths. The addition of external components is
unnecessary.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption (ICC) is at a minimum. Initiating any operation (by activating control
inputs) will immediately take the device out of the Power Down state.
The IDT72V3623/72V3643 are characterized for operation from 0°C
to 70°C. Industrial temperature range (-40°C to +85°C) is available by
special order. They are fabricated using high speed, submicron CMOS
technology.
3







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)