Gearing Clock. ICS9FG1201H Datasheet

ICS9FG1201H Clock. Datasheet pdf. Equivalent

ICS9FG1201H Datasheet
Recommendation ICS9FG1201H Datasheet
Part ICS9FG1201H
Description Frequency Gearing Clock
Feature ICS9FG1201H; DATASHEET Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD ICS9FG1201H Description The ICS.
Manufacture Renesas
Datasheet
Download ICS9FG1201H Datasheet




Renesas ICS9FG1201H
DATASHEET
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, &
FBD
ICS9FG1201H
Description
The ICS9FG1201H follows the Intel DB1200G Rev 1.0 Differential
Buffer Specification. This buffer provides 12 output clocks for CPU
Host Bus, PCI-Express, or Fully Buffered DIMM applications. The
outputs are configured with two groups. Both groups (DIF 9:0) and
(DIF 11:10) can be equal to or have a gear ratio to the input clock. A
differential CPU clock from a CK410B or CK410B+ main clock
generator, such as the ICS932S421, drives the ICS9FG1201. The
ICS9FG1201H can provide outputs up to 400MHz
Key Specifications
• DIF output cycle-to-cycle jitter < 50ps
• DIF output-to-output skew < 50ps within a group
• DIF output-to-output skew < 100ps across all outputs
• 56-pin SSOP/TSSOP package
• RoHS compliant packaging
Features/Benefits
• Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs)
• Power up default is all outputs in 1:1 mode
• DIF_(9:0) can be “gear-shifted” from the input CPU Host
Clock
• DIF_(11:10) can be “gear-shifted” from the input CPU Host
Clock
• Spread spectrum compatible
• Supports output clock frequencies up to 400 MHz
• 8 Selectable SMBus addresses
• SMBus address determines PLL or Bypass mode
Functional Block Diagram
OE#
OE(9:0)#
10
SPREAD
COMPATIBLE
PLL
CLK_IN
CLK_IN#
SPREAD
COMPATIBLE
PLL
HIGH_BW#
FS_A_410
VTT_PWRGD#/PD
SMB_A0
SMB_A1
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
CONTROL
LOGIC
GEAR
SHIFT
LOGIC
STOP
LOGIC
2
DIF(11:10)
GEAR
SHIFT
LOGIC
STOP
LOGIC
10
DIF(9:0)
IREF
IDTTM/ICSTM Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
1
1371F — 09/23/09



Renesas ICS9FG1201H
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
Pin Configuration
HIGH_BW# 1
56 VDDA
CLK_IN 2
55 GNDA
CLK_IN# 3
54 IREF
SMB_A0 4
53 OE10_11#
OE0# 5
52 DIF_11
DIF_0 6
51 DIF_11#
DIF_0# 7
50 VDD
OE1# 8
49 GND
DIF_1 9
48 DIF_10
DIF_1# 10
47 DIF_10#
VDD 11
46 FS_A_410
GND 12
45 VTT_PWRGD#/PD
DIF_2 13
44 OE9#
DIF_2# 14
43 DIF_9
OE2# 15
42 DIF_9#
DIF_3 16
41 OE8#
DIF_3# 17
40 DIF_8
OE3# 18
39 DIF_8#
DIF_4 19
38 VDD
DIF_4# 20
37 GND
OE4# 21
36 DIF_7
VDD 22
35 DIF_7#
GND 23
34 OE7#
DIF_5 24
33 DIF_6
DIF_5# 25
32 DIF_6#
OE5# 26
31 OE6#
SMB_A1 27
30 SMB_A2_PLLBYP#
SMBDAT 28
29 SMBCLK
56-pin SSOP & TSSOP
Functionality Table
FS_A_4101
CLK_IN (CPU FSB) DIF_(9:0) Output DIF_(11:10) Output
MHz
MHz
MHz
1
100.00
100.00
100.00
1
133.33
133.33
133.33
1
166.66
166.66
166.66
1 RESERVED
0
200.00
200.00
200.00
0
266.66
266.66
266.66
0
333.33
333.33
333.33
0
400.00
400.00
400.00
1. FS_A_410 is a low-threshold input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
IDTTM/ICSTM Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
2
1371F — 09/23/09



Renesas ICS9FG1201H
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
Power Groups
Pin Number
VDD
GND
56 55
11,22,38,50 12,23,37,49
Pin Description
Pin # Pin Name
1 HIGH_BW#
2 CLK_IN
3 CLK_IN#
4 SMB_A0
5 OE0#
6 DIF_0
7 DIF_0#
8 OE1#
9 DIF_1
10 DIF_1#
11 VDD
12 GND
13 DIF_2
14 DIF_2#
15 OE2#
16 DIF_3
17 DIF_3#
18 OE3#
19 DIF_4
20 DIF_4#
21 OE4#
22 VDD
23 GND
24 DIF_5
25 DIF_5#
26 OE5#
27 SMB_A1
28 SMBDAT
Description
Main PLL, Analog
DIF clocks
Type
IN
IN
IN
IN
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
PWR
PWR
OUT
OUT
IN
IN
I/O
Pin Description
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Input for reference clock.
"Complementary" reference clock input.
SMBus address bit 0 (LSB)
Active low input for enabling DIF pair 0.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 2.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 3.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 4
1 = tri-state outputs, 0 = enable outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
SMBus address bit 1
Data pin of SMBUS circuitry, 5V tolerant
IDTTM/ICSTM Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
3
1371F — 09/23/09







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)