STATIC RAM. 70V05L Datasheet

70V05L RAM. Datasheet pdf. Equivalent

70V05L Datasheet
Recommendation 70V05L Datasheet
Part 70V05L
Description DUAL-PORT STATIC RAM
Feature 70V05L; HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM 70V05S/L Features ◆ True Dual-Ported memory cells whic.
Manufacture Renesas
Datasheet
Download 70V05L Datasheet




Renesas 70V05L
HIGH-SPEED 3.3V
8K x 8 DUAL-PORT
STATIC RAM
70V05S/L
Features
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 15ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT70V05L
Active: 380mW (typ.)
Standby: 660μW (typ.)
IDT70V05 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 3.3V (±0.3V) power supply
Available in 68-pin PLCC and a 64-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O7L
BUSYL(1,2)
A12L
A0L
I/O
Control
I/O
Control
Address
Decoder
CEL
OEL
R/WL
13
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
13
SEML
INTL(2)
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
M/S
Address
Decoder
CER
OER
R/WR
1
,
I/O0R-I/O7R
BUSYR(1,2)
A12R
A0R
SEMR
INTR(2)
2942 drw 01
JUNE 2019
DSC 2941/12



Renesas 70V05L
70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Description
The IDT70V05 is a high-speed 8K x 8 Dual-Port Static RAM. The
IDT70V05 is designed to be used as a stand-alone 64K-bit Dual-Port
SRAM or as a combination MASTER/SLAVE Dual-Port SRAM for 16-bit-
or-morewordsystems. UsingtheIDTMASTER/SLAVEDual-PortSRAM
approach in 16-bit or wider memory system applications results in full-
speed, error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
Industrial and Commercial Temperature Ranges
reads or writes to any location in memory. An automatic power down
featurecontrolledby CEpermitstheon-chipcircuitryofeachporttoenter
a very low standby power mode.
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 400mW of power.
The IDT70V05 is packaged in a ceramic 68-pin PGA and PLCC
and a 64-pin thin quad flatpack (TQFP).
Pin Configurations(1,2,3)
I/O7R
N/C
OER
R/WR
SEMR
CER
N/C
N/C
VSS
A12R
A11R
A10R
A9R
A8R
A7R
A6R
A5R
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
27
28 8
29 7
30 6
31 5
32 4
33
34
35
70V05
PLG68(4)
3
2
1
36 68-Pin PLCC 68
37 Top View 67
38 66
39 65
40 64
41 63
42 62
43 61
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
I/O1L
I/O0L
N/C
OEL
R/WL
SEML
CEL
N/C
N/C
VDD
A12L
A11L
A10L
A9L
A8L
A7L
A6L
2941 drw 02
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J68-1 package body is approximately .95 in x .95 in x .17 in.
PN64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
A5L
A6L
A7L
A8L
A9L
A10L
A11L
A12L
VDD
N/C
CEL
SEML
R/WL
OEL
I/O0L
I/O1L
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49 32
50 31
51 30
52 29
53 28
54 27
55 26
56
70V05
PNG64(4)
25
57 24
58 23
59
64-Pin TQFP
Top View
22
60 21
61 20
62 19
63 18
64 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A5R
A6R
A7R
A8R
A9R
A10R
A11R
A12R
GND
N/C
CER
SEMR
R/WR
OER
I/O7R
I/O6R
2941 drw 03
6.242



Renesas 70V05L
70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Pin Configurations(1,2,3) (con't.)
Industrial and Commercial Temperature Ranges
12/03/01
11
51 50 48 46 44 42 40 38 36
A5L A4L A2L A0L BUSYL M/S INTR A1R A3R
53 52 49 47 45 43 41 39 37 35 34
10 A7L A6L A3L A1L INTL VSS BUSYR A0R A2R A4R A5R
55 54
09 A9L A8L
32 33
A7R A6R
57 56
08 A11L A10L
30 31
A9R A8R
59 58
07 VDD A12L
61 60
06 N/C N/C
63 62
05 SEML CEL
IDT70V05G
G68-1(4)
68-Pin PGA
Top View(5)
28 29
A11R A10R
26 27
VSS A12R
24 25
N/C N/C
65 64
04 OEL R/WL
22 23
SEMR CER
67 66
03 I/O0L N/C
20 21
OER R/WR
68 1 3 5 7 9 11 13 15 18 19
02 I/O1L I/O2L I/O4L VSS I/O7L VSS I/O1R VDD I/O4R I/O7R N/C
2 4 6 8 10 12 14 16 17
01 I/O3L I/O5L I/O6L VDD I/O0R I/O2R I/O3R I/O5R I/O6R
ABCDEFG H JK L
NOTES:
INDEX
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
2941 drw 04
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking.
Pin Names
Left Port
Right Port
CEL CER
R/WL R/WR
OEL
A0L - A12L
OER
A0R - A12R
I/O0L - I/O7L
I/O0R - I/O7R
SEML
SEMR
INTL INTR
BUSYL
BUSYR
M/S
VDD
VSS
6.342
Names
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power (3.3v)
Ground (0v)
2941 tbl 00







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