Clock Generator. 5X2503 Datasheet

5X2503 Generator. Datasheet pdf. Equivalent

5X2503 Datasheet
Recommendation 5X2503 Datasheet
Part 5X2503
Description MicroClock Programmable Clock Generator
Feature 5X2503; MicroClock Programmable Clock Generator 5X2503 Datasheet Description The 5X2503 MicroClock is a pr.
Manufacture Renesas
Datasheet
Download 5X2503 Datasheet




Renesas 5X2503
MicroClock Programmable Clock
Generator
5X2503
Datasheet
Description
The 5X2503 MicroClock is a programmable clock generator and is
intended for low-power, consumer, wearable and smart devices.
The 5X2503 device is a 3 PLL architecture design. Each PLL is
individually programmable, allowing for up to 3 unique frequency
outputs. The 5X2503 has built-in unique features such as Proactive
Power Saving (PPS) to deliver better system-level power
management.
An internal OTP memory allows the user to store the configuration in
the device without programming after power up. It can then be
reprogrammed again through the I2C interface.
The device has programmable VCO and PLL source selection
allowing the user to do power-performance optimization based on
the application requirements. A low-power 32.768kHz clock is
supported with only less than 2μA current consumption for system
RTC reference clock needs.
Typical Applications
SmartDevice, Handheld, Wearable applications
Consumer application crystal replacement
Block Diagram
Features
Configurable OE1 pin function as OE, PPS or DFC control
function
PPS: Proactive Power Saving features save power during the end
device power-down mode
DFC: Dynamic Frequency Control feature allows programming up
to 4 difference frequencies that switch dynamically
Integrated 26MHz crystal; no external input source requirement
Spread spectrum clock support to lower system EMI
I2C Interface
Output Features
3 LVCMOS outputs, 1MHz–125MHz
Low-power 32.768kHz clock supported
Wireless clock crystal integration and fan-out directly
Key Specifications
2μA operation for RTC clock 32.768kHz output
2.5 × 2.5 mm 12-DFN with crystal integration; small-form-factor
package
VDD1_8
VSS
Power
Monitor
POR
OSC
Calibration
32.768K
DCO
PLL1
PLL2
PLL3
Mux
&
Divider
OE1
OUT1
VDDOUT1
VSS
OUT2
VDDOUT2
VSS
OUT3
SEL_DFC/ SCL_DFC1/OE3
SDA_DFC0/OE2
I2C Engine
Overshoot Reduction
(ORT)
OTP memory (1 configuration )
Dynamic Frequency Control Logic (DFC)
Proactive Power Saving Logic (PPS)
©2017 Integrated Device Technology, Inc
1
December 18, 2017



Renesas 5X2503
Power Group
Power Supply
SE
DIV MUX PLL DCO
VDDOUT1
OUT1
VDDOUT2
OUT2/OUT3
V
VDD1_8
V V—V
Output Source Selection Register Setting Tables
OUT3 Source
Divider 3 (DIV3)
Divider 5 (DIV5)
Divider 1 (DIV1)
32.768kHz DCO
B35b7
0
0
1
1
B35b6
0
1
0
1
Xtal
V
OUT2 Source
Divider 3 (DIV3)
Divider 5 (DIV5)
Divider 1 (DIV1)
32.768kHz DCO
B35b5
0
0
1
1
OUT2 Source
Divider 3 (DIV3)
Divider 5 (DIV5)
Divider 1 (DIV1)
32.768kHz DCO
B35b3
0
0
1
1
DIV1 Source
PLL1
DIV4 seed
B35b7
0
1
B35b4
0
1
0
1
B35b2
0
1
0
1
B35b6
0
X
5X2503 Datasheet
©2017 Integrated Device Technology, Inc
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December 18, 2017



Renesas 5X2503
5X2503 Datasheet
Pin Assignments
Figure 1. Pin Assignments for 2.5 × 2.5 mm 12-DFN Package
SDA_DFC0/OE2
SEL_DFC/SCL_DFC1/OE3
VSS
VSS
VDD1_8
VDDOUT1
1
2
3
4
5
6
12
11
10
9
8
7
VSS
OUT3
VDDOUT2
OUT2
OE1
OUT1
2.5 × 2.5 mm 12-DFN
Pin Descriptions
Table 1. Pin Descriptions
Number
1
Name
SDA_DFC0/OE2
2 SEL_DFC/SCL_DFC1/OE3
3 VSS
4 VSS
5 VDD1_8
6 VDDOUT1
7 OUT1
8 OE1
9 OUT2
10 VDDOUT2
11 OUT3
12 VSS
– EPAD
Type
I/O
Input
Power
Power
Power
Power
Output
Input
Output
Power
Output
Power
GND
Description
I2C data pin; can be DFC0 function by OTP programming or selected by
SEL_DFC at power-on default. Output enable pin for OUT2.
I2C clock pin; can be DFC1 function by OTP programming selected by
SEL_DFC at power-on default. Output enable pin for OUT3.
Ground pin.
Ground pin.
1.8V power rail.
1.2V / 1.8V output clock power supply pin; supports OUT1.
1.2V / 1.8V LVCMOS clock output.
Output enable control 1.
1.8V LVCMOS clock output.
1.8V output clock power supply pin; supports OUT2/3.
1.8V LVCMOS clock output.
Ground pin.
Connect to ground pad.
Device Feature and Function
DFC – Dynamic Frequency Control
OTP programmable–4 different feedback fractional dividers (4 VCO frequencies) that apply to PLL2.
ORT (overshoot reduction) function will be applied automatically during the VCO frequency change.
Smooth frequency incremental or decremental from current VCO to targeted VCO base on DFC hardware pins selection.
©2017 Integrated Device Technology, Inc
3
December 18, 2017







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