Clock Synthesizer. 843S06 Datasheet

843S06 Synthesizer. Datasheet pdf. Equivalent

Part 843S06
Description PLL Clock Synthesizer
Feature Low Voltage, Low Skew, 1.244GHz PLL Clock Synthesizer 843S06 DATA SHEET GENERAL DESCRIPTION The 84.
Manufacture Renesas
Datasheet
Download 843S06 Datasheet



843S06
Low Voltage, Low Skew,
1.244GHz PLL Clock Synthesizer
843S06
DATA SHEET
GENERAL DESCRIPTION
The 843S06 is a low voltage, low skew 3.3V LVPECL Clock
Synthesizer. The device targets clock distribution in SDH/SONET
telecommunication systems but is well suited for a wide range
of applications requiring high performance high-speed clock
synthesis.
The device implements a fully integrated multiplying PLL
including:
An on-chip analog voltage controlled oscillator (VCO)
Phase-frequency detector
Programmable frequency dividers (prescalers)
The loop filter is external in order to optimize the PLL for different
applications.
As an option, the 843S06 may be operated with an ex-
ternal voltage controlled crystal oscillator for applications
demanding a high-Q oscillator.
FEATURES
Six differential 3.3V LVPECL outputs
1,244.16/622.08MHz; 1,244.16/622.08MHz
622.08/311.04MHz; 311.04/155.52MHz
155.52/77.76MHz;
77.76/38.88MHz
Three selectable differential reference clock inputs
Clock frequency range: 19MHz to 622MHz
REF_CLKx, nREF_CLKx pairs can accept the following differ-
ential input level: LVPECL
Intrinsic jitter: 0.017mUI @ 622MHz
RMS
Output skew: 200ps (maximum)
Optional external VCXO possible
Simple external loop filter
Lock detect output signal
Full 3.3V operating supply
Low power operation 0.6W (typical)
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
PIN ASSIGNMENT
BLOCK DIAGRAM
REF_CLK1:3
50Ω
VT1:3
50Ω
nREF_CLK1:3
Select
3:1
PFC
CP
CS RS
CHAP
VC
VCO
2.5GHz
VEE
REF_CLK1
nREF_CLK1
VT1
VT2
REF_CLK2
nREF_CLK2
SEL1
VCXO
VT3
REF_CLK3
nREF_CLK3
DCCAL VCXO
VEE
Div.
2, 4
VCCA
VCC
VEE
/2
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6
7
ICS843S06
31
30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
VEE
VCOSEL1
FOUTA
nFOUTA
OEAA
FOUTB
nFOUTB
OEAB
FOUT2
nFOUT2
OEA2
VEE
SEL1
SEL2
XOR
CHAP
Select
4:1
Div.
1, 2, 4, 8,
16, 32, 64
x7
Select
7:1
x7
VCOSEL1
VCOSEL2
C2
NLDET
NLOCK
x6
OEAx
FOUTx
nFOUTx
48-Lead TQFP, E-Pad
7mm x 7mm x 1.0mm
package body
Y Package
Top View
x3
SEL3:5
843S06 REVISION 11 10/23/15
1 ©2015 Integrated Device Technology, Inc.



843S06
843S06 DATA SHEET
FEATURES
The 843S06 comprises:
a low-noise analog VCO
a Phase-Frequency Detector
frequency dividers (prescalers)
a charge pump
into an integrated PLL frequency synthesizer. Careful design and
layout matching ensures short delay and minimum skew between
input reference clocks and outputs.
JITTER PERFORMANCE
The frequency of the input reference clock may range between
19.44MHz and 622.08MHz. Since changing the reference frequency
alters the loop-gain within the PLL it may be necessary to adjust
the loop-filter components when switching to a different reference
frequency in order to achieve ITU-T recommended performance.
PLL PROPAGATION DELAY
When the PLL is in lock, the Phase Frequency Detector aligns the
positive (low to high transition) flanks of the reference clock and
divided VCO clock on it’s inputs. These inputs are marked R and V
on Figure 1. This means the positive transition of any FOUTx output
clock is aligned with the positive transition of the reference clock
under the condition of equal reference clock frequency and FOUTx
output frequency, please refer to Figure 3. Figure 3 defines the PLL
propagation delay parameter (DOUT). Note that DOUT will change with
leakage currents drawn from the loop-filter, hence DOUT is loop-filter
dependant.
Figure 3 is an example for DOUT phase relationships.The REF_CLK[1:3]
input signals shown are in reference to FOUT2 output signals, both
running at Fx MHz with the PLL locked using the recommended
loop-filter and no excessive leakage current drawn from the charge
pump output. A skew of 200ps maximum is expected, (see Figure 4).
Skew over supply and temperature definitions are at any combination
of extremes. The expected skew values are only valid with the PLL
locked when using the recommended loop-filter. The Total Output
Uncertainty is DOUT + t ,skew (see Figures 3 and 4).
OUTPUT CLOCKS
The 843S06 is equipped with six LVPECL compatible output buf-
fers. Each of the output buffers is equipped with an LVTTL enable
pin that may be used to disable clock signals not in use for noise
reduction. Clock outputs are synchronized by the falling edge. The
phases of the clock output signals are aligned with less than 200ps
skew peak-to-peak between any two clock signals. Available clock
signals from the PLL are divide by 1 (signal FOUTA and by FOUTB),
divide by 2 (FOUT2), divide by 4 (FOUT4), divide by 8 (FOUT8)
and divide by 16 (FOUT16).
LOCK DETECT
The device outputs a signal NLDET that may be used to signal
whether or not the PLL is locked thus allowing fault diagnostics.The
NLDET outputs the result of an XOR operation of the signals input
to the phase-frequency detector. To be useful, this signal must be
filtered by a capacitor. The recommended value of this capacitor is
10nF. The filtered lock-detect signal is output as an LVTTL compat-
ible signal on the output NLOCK via a comparator.
PLL LOOP-FILTER
It has been chosen to locate the passive loop-filter components
externally to the device. This allows for easy optimization of the
loop-filter to different applications. The recommended loop-filter is
a simple first-order RC-Circuit as shown on Figure 1, resulting in a
second order, type 2 loop.
The values of R , C and C depend on the application. With respect
SS
P
to ITU-T recommended jitter performance, appropriate values for
R C and C have been determined to be R = 3.92kΩ, C = 0.22µF,
S, S
and C
=
P
1pF
for
input
frequency
of
S
155.52MHz;
and
R
S
=
9.09kΩ,
PS
C = 0.01µF, and C = 0 for input frequency of 19.44MHz.
SP
Note that the loop-filter should be terminated to the negative VCO
supply. An external VCXO might require a different termination point
for lowest point.
CHARGE PUMP POLARITY
When the PLL increases the VCO frequency, the charge pump pin
OCHP sinks current. That is, the voltage on the loop-filter capac-
itor drops to increase the oscillator frequency. So be aware, that
an external VCO must have a negative VCO constant in order to
achieve a stable lock.
ON-CHIP VCO POWER DOWN
When operated with an external VCXO the on-chip VCO should
be powered down for noise reduction. This is done by leaving V
CCA
open. See V pin description.
CCA
FREF
FVAR
RU
PFD
VD
NLDET
C2 10nF
NLOCK
CHAP VCO
OCHP
RS
CS
VCTL VCCA
CP +3.3V
FIGURE 1. APPLICATION DIAGRAM
LOW VOLTAGE, LOW SKEW,
1.244GHz PLL CLOCK SYNTHESIZER
2
REVISION 11 10/23/15





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