10-Quad Switch. 80KSW0005 Datasheet

80KSW0005 Switch. Datasheet pdf. Equivalent

Part 80KSW0005
Description 10-Quad Switch
Feature 10-Quad RapidIO® Switch Datasheet 80KSW0005 1 Device Overview The CPS-10Q (80KSW0005) is a serial .
Manufacture Renesas
Datasheet
Download 80KSW0005 Datasheet



80KSW0005
10-Quad
RapidIO® Switch
Datasheet
80KSW0005
1 Device Overview
The CPS-10Q (80KSW0005) is a serial RapidIO switch whose functionality is
central to routing packets for distribution among DSPs, processors, FPGAs,
other switches, or any other sRIO-based devices. The CPS-10Q supports serial
RapidIO packet switching (unicast, multicast, and an optional broadcast) from
any of its 16 input ports to any of its 16 output ports.
2 Features
u Interfaces - sRIO
40 bidirectional serial RapidIO (sRIO) lanes v 1.3
Port Speeds selectable: 3.125Gbps, 2.5Gbps, or 1.25Gbps
All lanes support short haul or long haul reach for each PHY speed
Configurable port count to up to 16 ports
Two enhanced quads can be configured as 4 1x ports or 1 4x ports
Supports standard 4 levels of priority
Error handling support: It allows error detection, logging and
response from all major functional blocks on the device.
u Interfaces - I2C
Provides I2C port for maintenance and error reporting
Master or Slave Operation
Master allows power-on configuration from external ROM
Master mode configuration with external image compressing and
checksum
u Performance
100 Gbps of peak switching bandwidth
Non-blocking data flow architecture within each sRIO priority
low latency for all packet length and load condition
Internal queuing buffer and retransmit buffer
Standard receiver based physical layer flow control
u Features
Configurable for cut-thru and store-and-forward
Device configurable through any of sRIO ports,
Im2Co,doersJTAG
Packet Trace function: It allows copying or filtering packets on a per-
port basis. Each port provides the ability to match the first 160 bits of
any packet against up to 4 programmable comparison values to copy
the packet to a programmable output trace port or drop it.
Supports up to 40 simultaneous multicast masks per each port
Support Broadcast
Port Loopback Debug Feature
Software assisted error recovery, supporting hot swap
Ports may be individually turned off to reduce power
PMON counters for monitor and diagnostics per port
Serdes physical diagnostic registers
Embedded PRBS generation and detection with programmable poly-
nomial cover error rate under all conditions
0.13um technology
Low power dissipation
Full JTAG Boundary Scan support (IEEE1149.1 & 1149.6)
Package: FCBGA 676-ball grid array, 27mm x 27mm, 1.0mm ball
pitch
3 Block Diagram
Ln0
Ln1
Ln2
Ln3
Ln4
Ln5
Ln6
Ln7
Ln8
Ln9
Ln10
Ln11
Ln12
Ln13
Ln14
Ln15
Ln16
Ln17
Ln18
Ln19
sRIO Q0
Standard
(1 port)
sRIO Q1
Standard
(1 port)
sRIO Q2
Standard
(1 port)
sRIO Q3
Standard
(1 port)
sRIO Q4
Enhanced
(1 or 4 ports)
2010 Integrated Device Technology, Inc. All rights reserved.
Serial RapidIO Switch
CPS-10Q
Maintenance
&
Error
Management
JTAG
Configuration
Figure 1 Block diagram
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I2C
sRIO Q9
Enhanced
(1 or 4 ports)
sRIO Q8
Standard
(1 port)
sRIO Q7
Standard
(1 port)
sRIO Q6
Standard
(1 port)
sRIO Q5
Standard
(1 port)
Ln39
Ln38
Ln37
Ln36
Ln35
Ln34
Ln33
Ln32
Ln31
Ln30
Ln29
Ln28
Ln27
Ln26
Ln25
Ln24
Ln23
Ln22
Ln21
Ln20
January 18, 2011
DSC 5697



80KSW0005
CPS-10Q
CPS-10Q Datasheet
4 Device Description
The CPS-10Q is optimized for cost-effective high performance RapidIO switching, typically used in embedded applications. Typical applications
include backplane switching and intensive signal processing where the switch is key to switching on the data path. These applications include wireless
infrastructure base station and RNCs, radar and sonar, and medical imaging. It can serve equally as backplane or linecard switch, supporting up to 16
ports. It is an end-point free (switch) device in an sRIO network.
The CPS-10Q receives packets from up to 16 ports. The device offers full support for normal switching as well as enhanced functions:
1) Normal Switching: All packets are switched in accordance with standard serial RapidIO specifications, with packet destination IDs determining
how the packet is routed.
Three major options exist within this category:
a. Multicast: If a Multicast ID is received, the CPS-10Q performs a multicast as defined in the sRIO multicast registers.
b. Unicast: specified by sRIO.
c. Maintenance packets: As specified by sRIO.
The CPS-10Q supports a peak throughput of 100 Gbps which is the line rate for 10 ports in 4x configuration, each at 10 Gbps (3.125 Gbps minus the
sRIO-defined 8b/10b encoding), and switches dynamically in accordance with the packet headers and priorities.
2) Enhanced functions
Enhanced features are provided for support of system debug. These features which are optional for the user consist of two major functions:
a. Packet Trace: The Packet Trace feature provides at-speed checking of the first 160 bits (header plus a portion of any payload) of every incom-
ing packet against user-defined comparison register values. The trace feature is available on all serial RapidIO ports, each acting indepen-
dently from one another. If the trace feature is enabled for a given port, every incoming packet is checked for a match against up to 4
comparison registers. In the event of a match, either of two possible user defined actions may take place:
i) not only does the packet route normally through the switch to its appropriate destination port, but this same packet is replicated and sent to
a “trace port.” The trace port itself may be any of the standard serial RapidIO ports. The port used for the trace port is defined by the user
through simple register configuration.
ii) the packet is dropped.
If there is no match, the packets route normally through the switch with no action taken.
The Packet Trace feature can be used during system bring-up and prototyping to identify particular packet types of interest to the user. It might
be used in security applications, where packets must be checked for either correct or incorrect tags in either of the header or payload. Identi-
fied (match) packets are then routed to the trace port for receipt by a host processor, which can perform an intervention at the software level.
b. Port Loopback: The CPS-10Q offers internal loopback for each port that may be used for system debug of the high speed sRIO ports. By
enabling loopback on a given port, packets sent to the port’s receiver are immediately looped back at the physical layer to the transmitter -
bypassing the higher logical or transport layers.
c. Broadcast: Each multicast mask can be configured so that the source port is included among the destination ports of that multicast operation.
The CPS-10Q can be programmed through any one or combination of sRIO, I2C, or JTAG. Note that any sRIO port may be used for programming.
The device can also configure itself on power-up by reading directly from ROM over I2C in master mode.
2010 Integrated Device Technology, Inc. All rights reserved.
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January 18, 2011





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