MK2049-36

3.3 VOLT COMMUNICATIONS CLOCK PLL DATASHEET MK2049-36 Description The MK2049-36 is a Phased Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications frequencies. This allows for the generation of clocks frequency-locked to an 8 kHz backplane clock, simplifying clock synchronization in communications systems. This part also has a jitter-attenuated Buffer capability. In this mode, the MK2049-36 is ideal for filtering jitter from clocks with high jitter. IDT can customize these devices for many other different frequencies. Contact your IDT representative for more details. Features Packaged in 20 pin SOIC Pb (lead) free package 3.3 V + 5% operation Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E Accepts multiple inputs: 8 kHz backplane clock or 10 to 50 MHz Locks to 8 kHz + 100 ppm (External mode) Buffer Mode allows jitter attenuation of 10 - 50 MHz input and x1/x0.5 or x1/x2 outputs Exact internal ratios enable zero ppm error Output clock rates include T1, E1, T3, E3, and OC3 submultiples See also the MK2049-34 and MK2049-45 Block Diagram EXTERNAL PULLABLE CRYSTAL INPUT REFERENCE CLOCK (TYPICALLY 8KHZ) 4 FREQUENCY SELECT VCXO-BASED PLL (MASTER CLOCK GENERATOR) FREQUENCY MULTIPLYING PLL CLOCK OUTPUT 2 CLOCK OUTP...