CLOCK PLL. MK2049-45 Datasheet

MK2049-45 PLL. Datasheet pdf. Equivalent

MK2049-45 Datasheet
Recommendation MK2049-45 Datasheet
Part MK2049-45
Description CLOCK PLL
Feature MK2049-45; 3.3 VOLT COMMUNICATIONS CLOCK PLL DATASHEET MK2049-45 Description The MK2049-45 is a dual Phase-Lo.
Manufacture Renesas
Datasheet
Download MK2049-45 Datasheet




Renesas MK2049-45
3.3 VOLT COMMUNICATIONS CLOCK PLL
DATASHEET
MK2049-45
Description
The MK2049-45 is a dual Phase-Locked Loop (PLL) device
which can provide frequency synthesis and jitter
attenuation. The first PLL is VCXO based and uses a
pullable crystal to track signal wander and attenuate input
jitter. The second PLL is a translator for frequency
multiplication. Basic configuration is determined by a
Mode/Frequency Selection Table. Loop bandwidth and
damping factor are programmable via external loop filter
component selection.
Buffer Mode accepts a 10 to 50MHz input and will provide a
jitter attenuated output at 0.5 x ICLK, 1 x ICLK or 2 x ICLK.
In this mode the MK2049-45 is ideal for filtering jitter from
high frequency clocks.
In External Mode, ICLK accepts an 8 kHz clock and will
produce output frequencies from a table of common
communciations clock rates, CLK and CLK/2. This allows
for the generation of clocks frequency-locked to an 8 kHz
backplane clock, simplifying clock synchronization in
communications systems.
The MK2049-45 can be dynamically switched between T1,
E1, T3, E3 outputs with the same 24.576 MHz crystal.
ICS can customize these devices for many other different
frequencies. Contact your ICS representative for more
details.
Features
Packaged in 20 pin SOIC
3.3 V + 5% operation
Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range, Phase
Transients, and Jitter Generation for Stratum 3, 4, and 4E
Accepts multiple inputs: 8 kHz backplane clock, or 10 to
50 MHz
Locks to 8 kHz + 100 ppm (External mode)
Buffer Mode allows jitter attenuation of 10 - 50 MHz input
and x1 / x0.5 or x1 / x2 outputs
Exact internal ratios enable zero ppm error
Output rates include T1, E1, T3, E3, and OC3
submultiples
Available in Pb (lead) free package
See also the MK2049-34 and MK2049-36
Not recommended for new designs. Use the
MK2049-45A.
Block Diagram
RSET
ISET
CP
CS
RS
CAP2
CL
CAP1 X1
CL Optional Crystal Load Caps
External Pullable Crystal
X2
ICLK
4
FS3:0
Reference
Divider
(used in buffer
mode only)
Phase
Detector
VCXO
PLL
VCXO
Charge
Pump
Feedback
Divider (N)
Divider Value
Look-up Table
Reference
Divider
VCO
Translator
PLL
Feedback
Divider
Output
Divider
Divide
by 2
CLK
CLK/2
8k
IDT™ / ICS™ 3.3 VOLT COMMUNICATIONS CLOCK PLL
1
MK2049-45 REV G 101904



Renesas MK2049-45
MK2049-45
3.3 VOLT COMMUNICATIONS CLOCK PLL
VCXO AND SYNTHESIZER
Pin Assignment
FS1
X2
X1
VDD
FCAP
VDD
GND
CLK
CLK/2
8k
1
2
3
4
5
6
7
8
9
10
20 FS0
19 RES
18 CAP2
17 GND
16 CAP1
15 VDD
14 GND
13 ICLK
12 FS3
11 FS2
Pin Descriptions
Pin
Number
1
Pin
Name
FS1
2 X2
3 X1
4 VDD
5 FCAP
6 VDD
7 GND
8 CLK
9 CLK/2
10 8k
11 FS2
12 FS3
13 ICLK
14 GND
15 VDD
16 CAP1
17 GND
Pin
Type
Input
Input
Input
Power
-
Power
Power
Output
Output
Output
Input
Input
Input
Power
Power
Loop
Filter
Power
Pin Description
Frequency select 1. Determines CLK input/outputs per table on page 2.
Internal pull-up resistor.
Crystal connection. Connect to a MHz crystal as shown in table on page 2.
Crystal connection. Connect to a MHz crystal as shown in table on page 2.
Power supply. Connect to +3.3V.
Filter capacitor. Connect a 1000 pF ceramic capacitor to ground.
Power supply. Connect to +3.3V.
Connect to ground
Clock output determined by status of FS3:0 per tables on page 2.
Clock output determined by status of FS3:0 per tables page 2. Always 1/2 of
CLK.
Recovered 8 kHz clock output.
Frequency select 2. Determines CLK input/outputs per table on page 2.
Internal pull-up resistor.
Frequency select 3. Determines CLK input/outputs per table on page 2.
Internal pull-up resistor.
Input clock connection. Connect to 8 kHz backplane or MHz clock.
Connect to ground.
Power Supply. Connect to +3.3V.
Connect the loop filter capacitors and resistor between this pin and CAP2.
Connect to ground.
IDT™ / ICS™ 3.3 VOLT COMMUNICATIONS CLOCK PLL
2
MK2049-45 REV G 101904



Renesas MK2049-45
MK2049-45
3.3 VOLT COMMUNICATIONS CLOCK PLL
VCXO AND SYNTHESIZER
Pin
Number
18
19
Pin
Name
CAP2
RES
Pin
Type
Loop
Filter
-
Pin Description
Connect the loop filter capacitors and resistor between this pin and CAP1.
Connect a resistor to ground. See table.
20 FS0 Input Frequency select 0. Determines CLK input/outputs per table on page 2.
Internal pull-up resistor.
Output Decoding Table - External Mode (MHz)
ICLK FS3 FS2 FS1 FS0
8 kHz 0 0 0 0
8 kHz 0 0 0 1
8 kHz 0 0 1 0
8 kHz 0 0 1 1
8 kHz 0 1 0 0
8 kHz 0 1 0 1
8 kHz 0 1 1 0
8 kHz 0 1 1 1
8 kHz 1 0 0 0
8 kHz 1 0 0 1
8 kHz 1 0 1 0
8 kHz 1 0 1 1
8 kHz 1 1 0 0
8 kHz 1 1 0 1
CLK/2
1.544
2.048
22.368
17.184
19.44
12.8
25.92
4.096
18.528
12.352
24.576
16.384
17.28
62.5
CLK
3.088
4.096
44.736
34.368
38.88
25.6
51.84
8.192
37.056
24.704
49.152
32.768
34.56
125
8k
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
Crystal
Used (MHz)
24.576
24.576
24.576
24.576
19.44
25.6
17.28
16.384
24.704
24.704
16.384
16.384
17.28
25
N
3072
3072
3072
3072
2430
3200
2160
2048
3088
3088
2048
2048
2160
3125
Output Decoding Table - Buffer Mode (MHz)
ICLK FS3 FS2 FS1 FS0 CLK/2
CLK
20 - 50
1
1
1
0
ICLK
2*ICLK
10 - 25
1
1
1
1
ICLK/2
ICLK
0 = connect directly to ground, 1 = connect directly to VDD
Crystal is connected to pins 2 and 3; clock input is applied to pin 13.
8k
N/A
N/A
Crystal
ICLK/2
ICLK
N
3
3
Functional Description
The MK2049-45 is a clock generator IC that generates an
output clock directly from an internal VCXO circuit which
works in conjunction with an external quartz crystal. The
VCXO is controlled by an internal PLL (Phase Locked Loop)
circuit, enabling the device to perform clock regeneration
from an input reference clock. The MK2049-45 is configured
to provide a high frequency communications reference clock
output from an 8 kHz input clock or to jitter attenuate and
buffer a high frequency input clock. There are 14 selectable
output frequencies and two buffer mode selections. Please
refer to the Output Clock Selection Table on Page 2.
Most typical PLL clock devices use an internal VCO (Voltage
Controlled Oscillator) for output clock generation. By using
a VCXO with an external crystal, the MK2049-45 is able to
generate a low jitter, low phase-noise output clock within a
IDT™ / ICS™ 3.3 VOLT COMMUNICATIONS CLOCK PLL
3
MK2049-45 REV G 101904







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