DDRII+ SRAM. R1QBA3636CBG Datasheet

R1QBA3636CBG SRAM. Datasheet pdf. Equivalent

Part R1QBA3636CBG
Description 36-Mbit DDRII+ SRAM
Feature R1QBA36**CB* / R1QEA36**CB* Series R1QBA3636CBG / R1QBA3618CBG / R1QBA3609CBG R1QEA3636CBG / R1QEA3.
Manufacture Renesas
Datasheet
Download R1QBA3636CBG Datasheet



R1QBA3636CBG
R1QBA36**CB* / R1QEA36**CB* Series
R1QBA3636CBG / R1QBA3618CBG / R1QBA3609CBG
R1QEA3636CBG / R1QEA3618CBG / R1QEA3609CBG
R1QHA3636CBG / R1QHA3618CBG / R1QHA3609CBG
R1QLA3636CBG / R1QLA3618CBG / R1QLA3609CBG
36-Mbit DDRII+ SRAM
2-word Burst
R10DS0159EJ0009
Rev. 0.09a
2011.09.14
Description
The R1Q#A3636 is a 1,048,576-word by 36-bit and the R1Q#A3618 is a 2,097,152-word by 18-bit synchronous
double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor
memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are
controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products
are suitable for applications which require synchronous operation, high speed, low voltage, high density and
wide bit configuration. These products are packaged in 165-pin plastic FBGA package.
# = B: Latency =2.5, w/o ODT
# = E: Latency =2.5, w/ ODT
# = H: Latency =2.0, w/o ODT
# = L: Latency =2.0, w/ ODT
Features
Power Supply
• 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)
Clock
• Fast clock cycle time for high bandwidth
• Two input clocks (K and /K) for precise DDR timing at clock rising edges only
• Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems
• Clock-stop capability with Ps restart
I/O
• Common data input/output bus
• Pipelined double data rate operation
• HSTL I/O
• User programmable output impedance
• DLL/PLL circuitry for wide output data valid window and future frequency scaling
• Data valid pin (QVLD) to indicate valid data on the output
Function
• Two-tick burst for low DDR transaction size
• Internally self-timed write control
• Simple control logic for easy depth expansion
• JTAG 1149.1 compatible test access port
Package
• 165 FBGA package (15 x 17 x 1.4 mm)
Notes: 1. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, IDT, Samsung, and Renesas Electronics Corp. (QDR Co-Development Team)
2. The specifications of this device are subject to change without notice. Please contact your nearest
Renesas Electronics Sales Office regarding specifications.
3. Refer to
"http://www.renesas.com/products/memory/fast_sram/qdr_sram/qdr_sram_root.jsp"
for the latest and detailed information.
4. Descriptions about x9 parts in this datasheet are just for reference.
Rev. 0.09a : 2011.09.14
R10DS0159EJ0009
PAGE : 1



R1QBA3636CBG
Common
R1QBA36**CB* / R1QEA36**CB* Series
Part Number Definition
Part Number Definition Table
No. 0 1 2 3 4 5 6 7 8 9 10 11 - 12 13 14 15 16
Example R 1 Q A A 4 4 3 6 R B G - 2 0 R B 0
0Q  %QOOGPVU
0Q  %QOOGPVU
0Q  %QOOGPVU
 4 4GPGUCU/GOQT[2TGHKZ
 # 8FF8
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3 3&4++$= ? . = ?
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3 3&4++$ .
3 &&4++$ .
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4
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+
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$) 2-)$)#ZOO
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# 2DHTGGCPF6TC[
$ 2DHTGGCPF6TC[
6 2DHTGGCPF6CRG4GGN
30 3&4++ $.
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`#`<
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= ?$$WTUVNGPIVJ $$WTUVNGPIVJ$$WTUVNGPIVJ
= ?.4GCF.CVGPE[ .4GCF.CVGPE[E[ENG.E[ENG.E[ENG
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= ?1&61PFKGVGTOKPCVKQP
2CEMCIG/CTMKPI0COG
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2DHTGGRCTVU/CTMKPI0COG2CTV0WODGT   2$(
 'ZCORNG 43##4$)42D(2DHTGGRCTVU
 'ZCORNG 43##4$)42$(2DHTGGRCTVU
2DHTGG4Q*5%QORNKCPEG.GXGN
2DHTGG4Q*5%QORNKCPEG.GXGN

Rev. 0.09a : 2011.09.14
R10DS0159EJ0009
PAGE : 2





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