DDRII+ SRAM. R1QBA3636CBG Datasheet

R1QBA3636CBG SRAM. Datasheet pdf. Equivalent

R1QBA3636CBG Datasheet
Recommendation R1QBA3636CBG Datasheet
Part R1QBA3636CBG
Description 36-Mbit DDRII+ SRAM
Feature R1QBA3636CBG; R1QBA36**CB* / R1QEA36**CB* Series R1QBA3636CBG / R1QBA3618CBG / R1QBA3609CBG R1QEA3636CBG / R1QEA3.
Manufacture Renesas
Datasheet
Download R1QBA3636CBG Datasheet




Renesas R1QBA3636CBG
R1QBA36**CB* / R1QEA36**CB* Series
R1QBA3636CBG / R1QBA3618CBG / R1QBA3609CBG
R1QEA3636CBG / R1QEA3618CBG / R1QEA3609CBG
R1QHA3636CBG / R1QHA3618CBG / R1QHA3609CBG
R1QLA3636CBG / R1QLA3618CBG / R1QLA3609CBG
36-Mbit DDRII+ SRAM
2-word Burst
R10DS0159EJ0009
Rev. 0.09a
2011.09.14
Description
The R1Q#A3636 is a 1,048,576-word by 36-bit and the R1Q#A3618 is a 2,097,152-word by 18-bit synchronous
double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor
memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are
controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products
are suitable for applications which require synchronous operation, high speed, low voltage, high density and
wide bit configuration. These products are packaged in 165-pin plastic FBGA package.
# = B: Latency =2.5, w/o ODT
# = E: Latency =2.5, w/ ODT
# = H: Latency =2.0, w/o ODT
# = L: Latency =2.0, w/ ODT
Features
Power Supply
• 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)
Clock
• Fast clock cycle time for high bandwidth
• Two input clocks (K and /K) for precise DDR timing at clock rising edges only
• Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems
• Clock-stop capability with Ps restart
I/O
• Common data input/output bus
• Pipelined double data rate operation
• HSTL I/O
• User programmable output impedance
• DLL/PLL circuitry for wide output data valid window and future frequency scaling
• Data valid pin (QVLD) to indicate valid data on the output
Function
• Two-tick burst for low DDR transaction size
• Internally self-timed write control
• Simple control logic for easy depth expansion
• JTAG 1149.1 compatible test access port
Package
• 165 FBGA package (15 x 17 x 1.4 mm)
Notes: 1. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, IDT, Samsung, and Renesas Electronics Corp. (QDR Co-Development Team)
2. The specifications of this device are subject to change without notice. Please contact your nearest
Renesas Electronics Sales Office regarding specifications.
3. Refer to
"http://www.renesas.com/products/memory/fast_sram/qdr_sram/qdr_sram_root.jsp"
for the latest and detailed information.
4. Descriptions about x9 parts in this datasheet are just for reference.
Rev. 0.09a : 2011.09.14
R10DS0159EJ0009
PAGE : 1



Renesas R1QBA3636CBG
Common
R1QBA36**CB* / R1QEA36**CB* Series
Part Number Definition
Part Number Definition Table
No. 0 1 2 3 4 5 6 7 8 9 10 11 - 12 13 14 15 16
Example R 1 Q A A 4 4 3 6 R B G - 2 0 R B 0
0Q  %QOOGPVU
0Q  %QOOGPVU
0Q  %QOOGPVU
 4 4GPGUCU/GOQT[2TGHKZ
 # 8FF8
 (TGSWGPE[/*\
3 3&4++$= ? . = ?
 &GPUKV[/D
 (TGSWGPE[/*\
3 3&4++$ .
3 &&4++$ .
  &GPUKV[/D
 &GPUKV[/D
 (TGSWGPE[/*\
 (TGSWGPE[/*\
3 &&4++$ .
 &GPUKV[/D
 (TGSWGPE[/*\
3 &&4++$5+1= ? .
 &CVCYKFVJDKV   (TGSWGPE[/*\
3# 3&4++ $.= ?
  &CVCYKFVJDKV
 (TGSWGPE[/*\
3$ &&4++ $.
 &CVCYKFVJDKV
 (TGSWGPE[/*\
3% &&4++ $.
4 UV)GPGTCVKQP
 (TGSWGPE[/*\
3& 3&4++ $.Y1&6= ?
# PF)GPGTCVKQP
 (TGSWGPE[/*\
3' &&4++ $.Y1&6
$ TF)GPGTCVKQP
 (TGSWGPE[/*\
 3( &&4++ $.Y1&6
3) 3&4++ $.
3* &&4++ $.
3, &&4++ $.
 % VJ)GPGTCVKQP
& VJ)GPGTCVKQP
' VJ)GPGTCVKQP
( VJ)GPGTCVKQP

4
%QOOGTEKCNVGOR
6CTCPIGé᳸é
+
+PFWUVTKCNVGOR
6CTCPIGé᳸é
3- 3&4++ $.Y1&6
3. &&4++ $.Y1&6
3/ &&4++ $.Y1&6

$) 2-)$)#ZOO
$# 2-)$)#ZOO

# 2DHTGGCPF6TC[
$ 2DHTGGCPF6TC[
6 2DHTGGCPF6CRG4GGN
30 3&4++ $.
5 2DHTGGCPF6CRG4GGN
32 3&4++ $.Y1&6

`#`<
QT0QPG
4GPGUCUKPVGTPCNWUG
0QVG
0QVG

0QVG
= ?$$WTUVNGPIVJ $$WTUVNGPIVJ$$WTUVNGPIVJ
= ?.4GCF.CVGPE[ .4GCF.CVGPE[E[ENG.E[ENG.E[ENG
= ?5+15GRCTCVG+1
= ?1&61PFKGVGTOKPCVKQP
2CEMCIG/CTMKPI0COG
2DHTGGRCTVU/CTMKPI0COG2CTV0WODGT 
2DHTGGRCTVU/CTMKPI0COG2CTV0WODGT   2$(
 'ZCORNG 43##4$)42D(2DHTGGRCTVU
 'ZCORNG 43##4$)42$(2DHTGGRCTVU
2DHTGG4Q*5%QORNKCPEG.GXGN
2DHTGG4Q*5%QORNKCPEG.GXGN

Rev. 0.09a : 2011.09.14
R10DS0159EJ0009
PAGE : 2



Renesas R1QBA3636CBG
hinS=00000.0000.0000.0000.0000---
11111.1111.1111.1111.1111---
00000.0000.0000.0000.0000---036M
R1QBA36**CB* / R1QEA36**CB* Series
36M QDR II+ / DDR II+ SRAM Lineup
- Renesas supports or plans to support the parts listed below.
No
17 QDRII+
18
20
21 DDRII+
23
24
26 QDRII+
27
29
30 DDRII+
32
33
35
36
QDRII+
38
39 DDRII+
41
42
44
45
QDRII+
47
48 DDRII+
50
51
B4
B2
B4
B4
B2
B4
B4
B2
B4
B4
B2
B4
QDR II+ / DDR II+
Frequency (max)
(MHz)
533 500 450 400 375
Cycle Time (min)
(ns)
1.875 2.00 2.22 2.50 2.66
Part NumberĄ yy ă -19 -20 -22 -25 -27
x18 R1Q A A36 18 C Bv- yy
x36 R1Q A A36 36 C Bv- yy
-19 -20 -22
x18 R1Q B A36 18 C Bv- yy
x36 R1Q B A36 36 C Bv- yy
-19 -20 -22
x18 R1Q C A36 18 C Bv- yy
x36 R1Q C A36 36 C Bv- yy
-19 -20 -22
x18 R1Q D A36 18 C Bv- yy
x36 R1Q D A36 36 C Bv- yy
-19 -20 -22
x18 R1Q E A36 18 C Bv- yy
x36 R1Q E A36 36 C Bv- yy
-19 -20 -22
x18 R1Q F A36 18 C Bv- yy
x36 R1Q F A36 36 C Bv- yy
-19 -20 -22
x18 R1Q G A36 18 C Bv- yy
x36 R1Q G A36 36 C Bv- yy
-25
x18 R1Q H A36 18 C Bv- yy
x36 R1Q H A36 36 C Bv- yy
-25
x18 R1Q J A36 18 C Bv- yy
x36 R1Q J A36 36 C Bv- yy
-25
x18 R1Q K A36 18 C Bv- yy
x36 R1Q K A36 36 C Bv- yy
-25
x18 R1Q L A36 18 C Bv- yy
x36 R1Q L A36 36 C Bv- yy
-25
x18 R1Q M A36 18 C Bv- yy
x36 R1Q M A36 36 C Bv- yy
-25
333
3.00
-30
QDR II / DDR II
333 300 250 200
3.00 3.30 4.00 5.00
-30 -33 -40 -50
Notes:
1. "yy" represents the speed bin. "R1QAA3636CBG-20" can operate at 500 MHz(max) of frequency, for example.
2. "v" represents the package size. If "v" = "G" then size is 15 x 17 mm, and if "v" = "A" then 13 x 15 mm.
3. The part which is not listed above is not supported, as of the day when this datasheet was issued,
in spite of the existence of the part number or datasheet.
Rev. 0.09a : 2011.09.14
R10DS0159EJ0009
PAGE : 3







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