10-BIT BUFFERS. CY74FCT827T Datasheet

CY74FCT827T BUFFERS. Datasheet pdf. Equivalent

Part CY74FCT827T
Description 10-BIT BUFFERS
Feature CY54FCT827T, CY74FCT827T 10-BIT BUFFERS WITH 3-STATE OUTPUTS SCCS034A – SEPTEMBER 1994 – REVISED OCT.
Manufacture etcTI
Datasheet
Download CY74FCT827T Datasheet



CY74FCT827T
CY54FCT827T, CY74FCT827T
10-BIT BUFFERS
WITH 3-STATE OUTPUTS
SCCS034A – SEPTEMBER 1994 – REVISED OCTOBER 2001
D Function, Pinout, and Drive Compatible
With FCT, F, and AM29827 Logic
D Reduced VOH (Typically = 3.3 V) Versions
of Equivalent FCT Functions
D Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D Ioff Supports Partial-Power-Down Mode
Operation
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D 3-State Outputs
D Matched Rise and Fall Times
D Fully Compatible With TTL Input and
Output Logic Levels
D CY54FCT827T
– 32-mA Output Sink Current
– 12-mA Output Source Current
D CY74FCT827T
– 64-mA Output Sink Current
– 32-mA Output Source Current
description
The ’FCT827T devices are 10-bit bus drivers that
provide high-performance bus-interface buffering
for wide data/address paths or buses carrying
parity. The 10-bit buffers have NANDed output
enables for maximum control flexibility. The
’FCT827T devices are designed for
high-capacitance-load drive capability, while
providing low-capacitance bus loading at both
inputs and outputs. All outputs are designed for
low-capacitance bus loading in the
high-impedance state.
CY74FCT827T . . . Q OR SO PACKAGE
(TOP VIEW)
OE1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 Y0
22 Y1
21 Y2
20 Y3
19 Y4
18 Y5
17 Y6
16 Y7
15 Y8
14 Y9
13 OE2
CY74FCT827T . . . L PACKAGE
(TOP VIEW)
4 3 2 1 28 27 26
D2 5
25 Y2
D3 6
24 Y3
D4 7
23 Y4
NC 8
22 NC
D5 9
21 Y5
D6 10
20 Y6
D7 11
19 Y7
12 13 14 15 16 17 18
NC – No internal connection
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2001, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1



CY74FCT827T
CY54FCT827T, CY74FCT827T
10-BIT BUFFERS
WITH 3-STATE OUTPUTS
SCCS034A SEPTEMBER 1994 REVISED OCTOBER 2001
ORDERING INFORMATION
TA
PACKAGE
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QSOP Q Tape and reel 4.4 CY74FCT827CTQCT
FCT827C
Tube
4.4 CY74FCT827CTSOC
SOIC SO
FCT827C
Tape and reel 4.4 CY74FCT827CTSOCT
40°C to 85°C
QSOP Q Tape and reel 8 CY74FCT827ATQCT
FCT827A
Tube
8 CY74FCT827ATSOC
SOIC SO
FCT827A
Tape and reel 8 CY74FCT827ATSOCT
55°C to 125°C LCC L
Tube
9 CY54FCT827ATLMB
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OE1
L
OE2
L
LL
D
L
H
OUTPUT
Y
L
H
FUNCTION
Transparent
HXX
XHX
Z
Z
3-state
H = High logic level, L = Low logic level, X = Dont care,
Z = High-impedance state
logic diagram (positive logic)
OE1
OE2
1
13
2
D0
23
Y0
Pin numbers shown are for the Q and SO packages.
To Nine Other Channels
absolute maximum rating over operating free-air temperature range (unless otherwise noted)
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Package thermal impedance, θJA (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W
SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 135°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and
functionaloperation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265





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