BUS-INTERFACE REGISTER. CY74FCT821T Datasheet

CY74FCT821T REGISTER. Datasheet pdf. Equivalent

Part CY74FCT821T
Description 10-BIT BUS-INTERFACE REGISTER
Feature D Function, Pinout, and Drive Compatible With FCT, F Logic, and AM29821 D Reduced VOH (Typically = 3.
Manufacture etcTI
Datasheet
Download CY74FCT821T Datasheet



CY74FCT821T
D Function, Pinout, and Drive Compatible
With FCT, F Logic, and AM29821
D Reduced VOH (Typically = 3.3 V) Version of
Equivalent FCT Functions
D Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D Ioff Supports Partial-Power-Down Mode
Operation
D Matched Rise and Fall Times
D Fully Compatible With TTL Input and
Output Logic Levels
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D 64-mA Output Sink Current
32-mA Output Source Current
D High-Speed Parallel Register With
Positive-Edge-Triggered D-Type Flip-Flops
D 3-State Outputs
CY74FCT821T
10-BIT BUS-INTERFACE REGISTER
WITH 3-STATE OUTPUTS
SCCS033B– MAY 1994 – REVISED NOVEMBER 2001
P, Q, OR SO PACKAGE
(TOP VIEW)
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 Y0
22 Y1
21 Y2
20 Y3
19 Y4
18 Y5
17 Y6
16 Y7
15 Y8
14 Y9
13 CP
description
This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and
provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT821T is a
10-bit-wide buffered version of the popular CY74FCT374 function. This device is ideal for use as an output port
requiring high IOL/IOH.
This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading
at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
PIN DESCRIPTION
NAME I/O
DESCRIPTION
D I D flip-flop data inputs
CP O Clock pulse for the register. Enters data into the register on the low-to-high clock transition.
Y O Register 3-state outputs
OE
I
Output control. When OE is high, the Y outputs are in the high-impedance state.
When OE is low, true register data is present at the Y outputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2001, Texas Instruments Incorporated
1



CY74FCT821T
CY74FCT821T
10-BIT BUS-INTERFACE REGISTER
WITH 3-STATE OUTPUTS
SCCS033BMAY 1994 REVISED NOVEMBER 2001
ORDERING INFORMATION
TA
PACKAGE
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QSOP Q Tape and reel
6
CY74FCT821CTQCT
FCT821C
Tube
6 CY74FCT821CTSOC
SOIC SO
FCT821C
Tape and reel 6 CY74FCT821CTSOCT
DIP P
Tube
7.5 CY74FCT821BTPC
CY74FCT821BTPC
40°C to 85°C
Tube
7.5 CY74FCT821BTSOC
SOIC SO
FCT821B
Tape and reel 7.5 CY74FCT821BTSOCT
QSOP Q Tape and reel
10 CY74FCT821ATQCT
FCT821A
Tube
10 CY74FCT821ATSOC
SOIC SO
FCT821A
Tape and reel 10 CY74FCT821ATSOCT
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OE D CP
INTERNAL
OUTPUTS
QY
FUNCTION
HXL Z
Z
HLLZ
HH H Z
LLLL
Load
L H HH
H = High logic level, L = Low logic level, X = Dont care,
= Low-to-high transition, Z = High-impedance state
logic diagram (positive logic)
1
OE
CP 13
D0 2
C0
Q
D0
23 Y0
To Nine Other Channels
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265





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