8-BIT REGISTERS. CY54FCT273T Datasheet

CY54FCT273T REGISTERS. Datasheet pdf. Equivalent

Part CY54FCT273T
Description 8-BIT REGISTERS
Feature D Function, Pinout, and Drive Compatible With FCT and F Logic D Reduced VOH (Typically = 3.3 V) Vers.
Manufacture etcTI
Total Page 12 Pages
Datasheet
Download CY54FCT273T Datasheet



CY54FCT273T
D Function, Pinout, and Drive Compatible
With FCT and F Logic
D Reduced VOH (Typically = 3.3 V) Versions
of Equivalent FCT Functions
D Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D Ioff Supports Partial-Power-Down Mode
Operation
D Matched Rise and Fall Times
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D Fully Compatible With TTL Input and
Output Logic Levels
D CY54FCT273T
– 32-mA Output Sink Current
– 12-mA Output Source Current
D CY74FCT273T
– 64-mA Output Sink Current
– 32-mA Output Source Current
description
The ’FCT273T devices consist of eight
edge-triggered D-type flip-flops with individual
D inputs and Q outputs. The common
buffered-clock (CP) and master-reset (MR) inputs
load and reset all flip-flops simultaneously. These
devices are edge-triggered registers. The state of
each D input (one setup time before the
low-to-high clock transition) is transferred to the
corresponding flip-flop’s Q output. All outputs are
forced low by a low logic level on the MR input.
This device is fully specified for
partial-power-down applications using Ioff. The Ioff
circuitry disables the outputs, preventing
damaging current backflow through the device
when it is powered down.
CY54FCT273T, CY74FCT273T
8-BIT REGISTERS
SCCS020A – MARCH 1995 – REVISED OCTOBER 2001
CY54FCT273T . . . D PACKAGE
CY74FCT273T . . . Q OR SO PACKAGE
(TOP VIEW)
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
CY54FCT273T . . . L PACKAGE
(TOP VIEW)
3 2 1 20 19
D1 4
18 D7
Q1 5
17 D6
Q2 6
16 Q6
D2 7
15 Q5
D3 8
14 D5
9 10 11 12 13
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2001, Texas Instruments Incorporated
1



CY54FCT273T
CY54FCT273T, CY74FCT273T
8-BIT REGISTERS
SCCS020A MARCH 1995 REVISED OCTOBER 2001
ORDERING INFORMATION
TA
PACKAGE
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QSOP Q Tape and reel 5.8 CY74FCT273CTQCT FCT273C
Tube
5.8 CY74FCT273CTSOC
SOIC SO
FCT273C
Tape and reel 5.8 CY74FCT273CTSOCT
QSOP Q Tape and reel 7.2 CY74FCT273ATQCT FCT273A
40°C to 85°C
Tube
7.2 CY74FCT273ATSOC
SOIC SO
FCT273A
Tape and reel 7.2 CY74FCT273ATSOCT
QSOP Q Tape and reel
13 CY74FCT273TQCT
FCT273
Tube
13 CY74FCT273TSOC
SOIC SO
FCT273
Tape and reel 13 CY74FCT273TSOCT
55°C to 125°C LCC L
Tube
8.3 CY54FCT273ATLMB
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
MR CP
D
OUTPUT OPERATING
Q MODE
LXX
L Reset (clear)
Hh
H
Load 1
H
l
L
Load 0
H = High logic level steady state, h = High logic level one
setup time prior to low-to-high clock transition, L = Low
logic level steady state, l = Low logic level one setup time
prior to the low-to-high transition, X = Dont care,
= Low-to-high clock transition
logic diagram (positive logic)
D0 D1 D2 D3 D4 D5 D6 D7
3 4 7 8 13 14 17 18
11
CP
1
MR
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
2 5 6 9 12 15 16 19
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265





@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)