CY54FCT273T

D Function, Pinout, and Drive Compatible With FCT and F Logic D Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions D Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics D Ioff Supports Partial-Power-Down Mode Operation D Matched Rise and Fall Times D ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) D Fully Compatible With TTL Input and Output Logic Levels D CY54FCT273T – 32-mA Output Sink Current – 12-mA Output Source Current D CY74FCT273T – 64-mA Output Sink Current – 32-mA Output Source Current description The ’FCT273T devices consist of eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered-clock (CP) and master-reset (MR) inputs load and reset all flip-flops simultaneously. These devices are edge-triggered registers. The state of each D input (one setup time before the low-to-high clock transition) is transferred to the corresponding flip-flop’s Q output. All outputs are forced low by a low logic level on the MR input. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Q3 D0 GND Q0 CP MR Q4 D4 Q7 CY54FCT273T, CY74FCT273T 8-BIT REGISTERS SCCS020A – MARCH 1995 – REVISED OCTOBER 2001 CY54FCT273T . . . D PACKAGE CY74FCT273T . . . Q OR SO PACKAGE (TOP VIE...