8-BIT REGISTERS. CY74FCT374T Datasheet

CY74FCT374T REGISTERS. Datasheet pdf. Equivalent

Part CY74FCT374T
Description 8-BIT REGISTERS
Feature D Function, Pinout, and Drive Compatible With FCT and F Logic D Reduced VOH (Typically = 3.3 V) Vers.
Manufacture etcTI
Datasheet
Download CY74FCT374T Datasheet



CY74FCT374T
D Function, Pinout, and Drive Compatible
With FCT and F Logic
D Reduced VOH (Typically = 3.3 V) Versions
of Equivalent FCT Functions
D Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D Ioff Supports Partial-Power-Down Mode
Operation
D Matched Rise and Fall Times
D Fully Compatible With TTL Input and
Output Logic Levels
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D Edge-Triggered D-Type Inputs
D 250-MHz Typical Switching Rate
D CY54FCT374T
– 32-mA Output Sink Current
– 12-mA Output Source Current
D CY74FCT374T
– 64-mA Output Sink Current
– 32-mA Output Source Current
D 3-State Outputs
CY54FCT374T, CY74FCT374T
8-BIT REGISTERS
WITH 3-STATE OUTPUTS
SCCS022A – MAY 1994 – REVISED OCTOBER 2001
CY54FCT374T . . . D PACKAGE
CY74FCT374T . . . P, Q, OR SO PACKAGE
(TOP VIEW)
OE
O0
D0
D1
O1
O2
D2
D3
O3
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 O7
18 D7
17 D6
16 O6
15 O5
14 D5
13 D4
12 O4
11 CP
CY54FCT374T . . . L PACKAGE
(TOP VIEW)
D1
3 2 1 20 19
4 18
D7
O1 5
17 D6
O2 6
16 O6
D2 7
15 O5
D3
8 14
9 10 11 12 13
D5
description
The ’FCT374T devices are high-speed, low-power, octal D-type flip-flops, featuring separate D-type inputs for
each flip-flop. These devices have 3-state outputs for bus-oriented applications. A buffered clock (CP) and
output-enable (OE) inputs are common to all flip-flops. The eight flip-flops in the ’FCT374T store the state of
their individual D inputs that meet the setup-time and hold-time requirements on the low-to-high CP transition.
When OE is low, the contents of the eight flip-flops are available at the outputs. When OE is high, the outputs
are in the high-impedance state. The state of OE does not affect the state of the flip-flops.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2001, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1



CY74FCT374T
CY54FCT374T, CY74FCT374T
8-BIT REGISTERS
WITH 3-STATE OUTPUTS
SCCS022A MAY 1994 REVISED OCTOBER 2001
ORDERING INFORMATION
TA
PACKAGE
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QSOP Q Tape and reel 5.2 CY74FCT374CTQCT
FCT374C
Tube
5.2 CY74FCT374CTSOC
SOIC SO
FCT374C
Tape and reel 5.2 CY74FCT374CTSOCT
DIP P
Tube
6.5 CY74FCT374ATPC
CY74FCT374ATPC
QSOP Q Tape and reel 6.5 CY74FCT374ATQCT
FCT374A
40°C to 85°C
Tube
6.5 CY74FCT374ATSOC
SOIC SO
FCT374A
Tape and reel 6.5 CY74FCT374ATSOCT
QSOP Q Tape and reel 10 CY74FCT374TQCT
FCT374
Tube
10 CY74FCT374TSOC
SOIC SO
Tape and reel 10 CY74FCT374TSOCT
FCT374
CDIP D Tube
6.2 CY54FCT374CTDMB
LCC L
Tube
6.2 CY54FCT374CTLMB
CDIP D
55°C to 125°C
LCC L
Tube
Tube
7.2 CY54FCT374ATDMB
7.2 CY54FCT374ATLMB
CDIP D Tube
11 CY54FCT374TDMB
LCC L
Tube
11 CY54FCT374TLMB
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available
at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
D CP OE
OUTPUT
O
HL
H
LL
L
XXH
Z
H = High logic level, L = Low logic level,
X = Dont care, Z = High-impedance state,
= Low-to-high clock transition
logic diagram (positive logic)
OE 1
CP 11
3
D0
C1
Q
1D
2
O0
To Seven Other Channels
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265





@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)