8-BIT LATCHES. CY54FCT573T Datasheet

CY54FCT573T LATCHES. Datasheet pdf. Equivalent

Part CY54FCT573T
Description 8-BIT LATCHES
Feature D Function and Pinout Compatible With FCT and F Logic D Reduced VOH (Typically = 3.3 V) Versions of .
Manufacture etcTI
Datasheet
Download CY54FCT573T Datasheet



CY54FCT573T
D Function and Pinout Compatible With FCT
and F Logic
D Reduced VOH (Typically = 3.3 V) Versions
of Equivalent FCT Functions
D Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D Ioff Supports Partial-Power-Down Mode
Operation
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D Matched Rise and Fall Times
D Fully Compatible With TTL Input and
Output Logic Levels
D 3-State Outputs
D CY54FCT573T
– 32-mA Output Sink Current
– 12-mA Output Source Current
D CY74FCT573T
– 64-mA Output Sink Current
– 32-mA Output Source Current
CY54FCT573T, CY74FCT573T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS068 – OCTOBER 2001
CY54FCT573T . . . D PACKAGE
CY74FCT573T . . . P, Q, OR SO PACKAGE
(TOP VIEW)
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 O0
18 O1
17 O2
16 O3
15 O4
14 O5
13 O6
12 O7
11 LE
description
The ’FCT573T devices consist of eight latches with 3-state outputs for bus-organized applications. When the
latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup
times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE)
input is low. When OE is high, the bus output is in the high-impedance state. In this mode, data can be entered
into the latches. The ’FCT573T devices are identical to the ’FCT373T devices, except for the flow-through
pinout of the ’FCT573T, which simplifies board design.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2001, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1



CY54FCT573T
CY54FCT573T, CY74FCT573T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS068 OCTOBER 2001
ORDERING INFORMATION
TA
PACKAGE
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QSOP Q Tape and reel
4.7 CY74FCT573CTQCT
FCT573C
Tube
4.7 CY74FCT573CTSOC
SOIC SO
FCT573C
Tape and reel 4.7 CY74FCT573CTSOCT
DIP P
Tube
5.2 CY74FCT573ATPC
CY74FCT573ATPC
QSOP Q Tape and reel 5.2 CY74FCT573ATQCT
FCT573A
40°C to 85°C
Tube
5.2 CY74FCT573ATSOC
SOIC SO
FCT573A
Tape and reel 5.2 CY74FCT573ATSOCT
QSOP Q Tape and reel 8 CY74FCT573TQCT
FCT573
Tube
8 CY74FCT573TSOC
SOIC SO
FCT573
Tape and reel 8 CY74FCT573TSOCT
55°C to 125°C CDIP D
Tube
8.5 CY54FCT573ATLMB
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
logic diagram (positive logic)
FUNCTION TABLE
INPUTS
OE LE
D
OUTPUT
O
L HH
H
LHL
L
LLX
HXX
Q0
Z
H = High logic level, L = Low logic level,
X = Dont care, Z = High-impedance state,
Qn = Previous state of flip flops (Qn1)
1
OE
LE 11
2
D0
CP
Q
D
19
O0
To Seven Other Channels
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265





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