CY54FCT841T

D Function, Pinout, and Drive Compatible With FCT, F, and AM29841 Logic D Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions D Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics D Ioff Supports Partial-Power-Down Mode Operation D Matched Rise and Fall Times D ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) D Fully Compatible With TTL Input and Output Logic Levels D High-Speed Parallel Latches D Buffered Common Latch-Enable Input D 3-State Outputs D CY54FCT841T – 32-mA Output Sink Current – 12-mA Output Source Current D CY74FCT841T – 64-mA Output Sink Current – 32-mA Output Source Current CY54FCT841T, CY74FCT841T 10-BIT LATCHES WITH 3-STATE OUTPUTS SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001 CY54FCT841T . . . D PACKAGE CY74FCT841T . . . P, Q, OR SO PACKAGE (TOP VIEW) OE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 VCC 23 Y0 22 Y1 21 Y2 20 Y3 19 Y4 18 Y5 17 Y6 16 Y7 15 Y8 14 Y9 13 LE description The ’FCT841T bus-interface latches are designed to eliminate additional packages required to buffer existing latches and provide additional data width for wider address/data paths or buses carrying parity. The ’FCT841T devices are buffered 10-bit-wide versions of the FCT373 function. The ’FCT841T devices’ high-performance interface is designed for high-capacitance-load drive capability, while providing low-capacitance bus loading...