10-BIT LATCHES. CY74FCT841T Datasheet

CY74FCT841T LATCHES. Datasheet pdf. Equivalent

Part CY74FCT841T
Description 10-BIT LATCHES
Feature D Function, Pinout, and Drive Compatible With FCT, F, and AM29841 Logic D Reduced VOH (Typically = 3.
Manufacture etcTI
Datasheet
Download CY74FCT841T Datasheet



CY74FCT841T
D Function, Pinout, and Drive Compatible
With FCT, F, and AM29841 Logic
D Reduced VOH (Typically = 3.3 V) Versions of
Equivalent FCT Functions
D Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D Ioff Supports Partial-Power-Down Mode
Operation
D Matched Rise and Fall Times
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D Fully Compatible With TTL Input and
Output Logic Levels
D High-Speed Parallel Latches
D Buffered Common Latch-Enable Input
D 3-State Outputs
D CY54FCT841T
– 32-mA Output Sink Current
– 12-mA Output Source Current
D CY74FCT841T
– 64-mA Output Sink Current
– 32-mA Output Source Current
CY54FCT841T, CY74FCT841T
10-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001
CY54FCT841T . . . D PACKAGE
CY74FCT841T . . . P, Q, OR SO PACKAGE
(TOP VIEW)
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 Y0
22 Y1
21 Y2
20 Y3
19 Y4
18 Y5
17 Y6
16 Y7
15 Y8
14 Y9
13 LE
description
The ’FCT841T bus-interface latches are designed to eliminate additional packages required to buffer existing
latches and provide additional data width for wider address/data paths or buses carrying parity. The ’FCT841T
devices are buffered 10-bit-wide versions of the FCT373 function.
The ’FCT841T devices’ high-performance interface is designed for high-capacitance-load drive capability, while
providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance
bus loading in the high-impedance state.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
NAME
D
LE
Y
OE
PIN DESCRIPTION
I/O DESCRIPTION
I Latch data inputs
I
Latch-enable input. The latches are transparent when LE is high.
Input data is latched on the high-to-low transition.
O 3-state latch outputs
I
Output-enable control. When OE is low, the outputs are enabled.
When OE is high, the outputs are in the high-impedance (off) state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2001, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1



CY74FCT841T
CY54FCT841T, CY74FCT841T
10-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS035A SEPTEMBER 1994 REVISED OCTOBER 2001
ORDERING INFORMATION
TA
PACKAGE
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QSOP Q Tape and reel
5.5
CY74FCT841CTQCT FCT841C
40°C to 85°C
SOIC SO
DIP P
Tube
Tape and reel
Tube
5.5
5.5
6.5
CY74FCT841CTSOC
CY74FCT841CTSOCT
CY74FCT841BTPC
FCT841C
CY74FCT841BTPC
SOIC SO
Tube
Tape and reel
9
9
CY74FCT841ATSOC
CY74FCT841ATSOCT
FCT841A
55°C to 125°C CDIP D Tube
10 CY54FCT841ATDMB
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OE LE
D
INTERNAL
OUTPUTS
OY
FUNCTION
HXXXZ
HHL L Z
Z
HHHHZ
H L X NC Z
Latched (Z)
LHL L L
L HHHH
Transparent
L L X NC NC
Latched
H = High logic level, L = Low logic level, X = Dont care,
NC = No change, Z = High-impedance state
logic diagram (positive logic)
1
OE
13
LE
2
D0
LE
Q
D
23
Y0
To Nine Other Channels
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265





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