REGISTERED TRANSCEIVERS. CY74FCT646T Datasheet

CY74FCT646T TRANSCEIVERS. Datasheet pdf. Equivalent

Part CY74FCT646T
Description 8-BIT REGISTERED TRANSCEIVERS
Feature CY54FCT646T, CY74FCT646T 8-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCCS031A – JULY 1994 – R.
Manufacture etcTI
Total Page 14 Pages
Datasheet
Download CY74FCT646T Datasheet



CY74FCT646T
CY54FCT646T, CY74FCT646T
8-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS031A – JULY 1994 – REVISED OCTOBER 2001
D Function, Pinout, and Drive Compatible
With FCT and F Logic
D Reduced VOH (Typically = 3.3 V) Versions
of Equivalent FCT Functions
D Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D Ioff Supports Partial-Power-Down Mode
Operation
D Matched Rise and Fall Times
D Fully Compatible With TTL Input and
Output Logic Levels
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
CY54FCT646T . . . D PACKAGE
CY74FCT646T . . . Q OR SO PACKAGE
(TOP VIEW)
CPAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 CPBA
22 SBA
21 G
20 B1
19 B2
18 B3
17 B4
16 B5
15 B6
14 B7
13 B8
– 1000-V Charged-Device Model (C101)
D Independent Register for A and B Buses
D CY54FCT646T
CY54FCT646T . . . L PACKAGE
(TOP VIEW)
– 48-mA Output Sink Current
– 12-mA Output Source Current
D CY74FCT646T
– 64-mA Output Sink Current
– 32-mA Output Source Current
D 3-State Outputs
4 3 2 1 28 27 26
A1 5
25 G
A2 6
24 B1
A3 7
23 B2
NC 8
22 NC
description
The ’FCT646T devices consist of a bus
transceiver circuit with 3-state, D-type flip-flops,
A4 9
21 B3
A5 10
20 B4
A6 11
19 B5
12 13 14 15 16 17 18
and control circuitry arranged for multiplexed
transmission of data directly from the input bus or
from the internal registers. Data on the A or B bus
is clocked into the registers as the appropriate
NC – No internal connection
clock pin goes to a high logic level. Output-enable (G) and direction (DIR) inputs control the transceiver function.
In the transceiver mode,data present at the high-impedance port can be stored in either the A or B register, or
in both. Select controls (SAB, SBA) can multiplex stored and real-time (transparent mode) data. DIR determines
which bus receives data when G is low. In the isolation mode (G is high), A data can be stored in the B register
and/or B data can be stored in the A register.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2001, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1



CY74FCT646T
CY54FCT646T, CY74FCT646T
8-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS031A JULY 1994 REVISED OCTOBER 2001
NAME
A
B
CPAB, CPBA
SAB, SBA
DIR, G
PIN DESCRIPTION
DESCRIPTION
Data register A inputs, data register B outputs
Data register B inputs, data register A outputs
Clock-pulse inputs
Output data-source-select inputs
Output-enable inputs
ORDERING INFORMATION
TA
PACKAGE
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QSOP Q Tape and reel
5.4 CY74FCT646CTQCT FCT646C
SOIC SO
Tube
Tape and reel
5.4 CY74FCT646CTSOC
FCT646C
5.4 CY74FCT646CTSOCT
QSOP Q Tape and reel
6.3 CY74FCT646ATQCT FCT646A
40°C to 85°C
SOIC SO
Tube
Tape and reel
6.3 CY74FCT646ATSOC
FCT646A
6.3 CY74FCT646ATSOCT
QSOP Q Tape and reel 9 CY74FCT646TQCT FCT646
Tube
9 CY74FCT646TSOC
SOIC SO
FCT646
Tape and reel 9 CY74FCT646TSOCT
LCC L
Tube
6 CY54FCT646CTLMB
55°C to 125°C
CDIP D
LCC L
Tube
Tube
Tube
7.7 CY54FCT646ATDMB
7.7 CY54FCT646ATLMB
11 CY54FCT646TLMB
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
DATA I/O
G DIR CPAB CPBA SAB SBA A1A8 B1B8
OPERATION
OR FUNCTION
H X H or L H or L X X Input Input Isolation
HX
X X Input Input Store A and B data
LL
X
X X L Output Input Real-time B data to A bus
LL
X H or L X
H Output Input Stored B data to A bus
LH
X
X
L
X
Input
Output Real-time A data to B bus
L
H H or L
X
H
X
Input
Output Stored A data to B bus
H = High logic level, L = Low logic level, = Low-to-high transition, X = Dont care
The data output functions can be enabled or disabled by various signals at the G or DIR inputs. Data input
functions always are enabled, i.e., data at the bus pins is stored on every low-to-high transition of the
clock inputs.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265





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