REGISTERED TRANSCEIVER. CY74FCT652T Datasheet

CY74FCT652T TRANSCEIVER. Datasheet pdf. Equivalent

Part CY74FCT652T
Description 8-BIT REGISTERED TRANSCEIVER
Feature D Function, Pinout, and Drive Compatible With FCT and F Logic D Reduced VOH (Typically = 3.3 V) Vers.
Manufacture etcTI
Datasheet
Download CY74FCT652T Datasheet



CY74FCT652T
D Function, Pinout, and Drive Compatible
With FCT and F Logic
D Reduced VOH (Typically = 3.3 V) Version of
Equivalent FCT Functions
D Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D Ioff Supports Partial-Power-Down Mode
Operation
D Matched Rise and Fall Times
D Fully Compatible With TTL Input and
Output Logic Levels
D 64-mA Output Sink Current
32-mA Output Source Current
D Independent Register for A and B Buses
D Multiplexed Real-Time and Stored Data
Transfer
D 3-State Outputs
CY74FCT652T
8-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS032B – SEPTEMBER 1994 – REVISED OCTOBER 2001
Q OR SO PACKAGE
(TOP VIEW)
CPAB
SAB
GAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 CPBA
22 SBA
21 GBA
20 B1
19 B2
18 B3
17 B4
16 B5
15 B6
14 B7
13 B8
description
The CY74FCT652T consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus or from the internal storage registers. GAB and GBA
inputs control the transceiver functions. Select-control (SAB and SBA) inputs select either real-time or
stored-data transfer. The circuitry used for select control eliminates the typical decoding glitch that occurs in
a multiplexer during the transition between stored and real-time data. A low input level selects real-time data,
and a high input level selects stored data.
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions
of the appropriate clock (CPAB or CPBA) inputs, regardless of the select or enable levels of the control pins.
When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the internal
D-type flip-flops by simultaneously enabling GAB and GBA. In this configuration, each output reinforces its
input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus
lines remains at its last state.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2001, Texas Instruments Incorporated
1



CY74FCT652T
CY74FCT652T
8-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS032B SEPTEMBER 1994 REVISED OCTOBER 2001
ORDERING INFORMATION
TA
PACKAGE†
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QSOP Q Tape and reel 5.4 CY74FCT652CTQCT FCT652C
Tube
5.4 CY74FCT652CTSOC
SOIC SO
FCT652C
Tape and reel 5.4 CY74FCT652CTSOCT
40°C to 85°C QSOP Q Tape and reel 6.3 CY74FCT652ATQCT FCT652A
Tube
6.3 CY74FCT652ATSOC
SOIC SO
FCT652A
Tape and reel 6.3 CY74FCT652ATSOCT
QSOP Q Tape and reel
9
CY74FCT652TQCT
FCT652
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
GAB
L
GBA
H
INPUTS
CPAB CPBA
H or L H or L
SAB
X
SBA
X
DATA I/O
A1–A8
Input
B1–B8
Input
OPERATION OR
FUNCTION
Isolation
LH
XX
Input
Input
Store A and B data
XH
H or L X
X
Input
Unspecified§ Store A, hold B
HH
XX
Input
Output
Store A in both registers
L
X H or L
X X Unspecified§
Input
Hold A, store B
LL
X XOutput
Input
Store B in both registers
LL
X
X XL
Output
Input
Real-time B data to A bus
LL
X H or L X
H
Output
Input
Stored B data to A bus
HH
X
X LX
Input
Output
Real-time A data to B bus
H
H H or L
X
HX
Input
Output
Stored A data to B bus
H L H or L H or L H H
Output
Output
Stored A data to B bus and
Stored B data to A bus
H = High logic level, L = Low logic level, X = Dont care, = Low-to-high transition
Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered in order to load both
registers.
§ The data output functions can be enabled or disabled by various signals at the GAB and GBA inputs. Data input functions
always are enabled, i.e., data at the bus pins are stored on every low-to-high transition of the clock inputs.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265





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