Ultralow-Power ADC. ADS4249 Datasheet

ADS4249 ADC. Datasheet pdf. Equivalent

Part ADS4249
Description Ultralow-Power ADC
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ADS4249
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ADS4249
SBAS534E – JULY 2011 – REVISED JANUARY 2016
ADS4249 Dual-Channel, 14-Bit, 250-MSPS Ultralow-Power ADC
1 Features
1 Maximum Sample Rate: 250 MSPS
• Ultra-Low Power with Single 1.8-V Supply:
– 560-mW Total Power at 250 MSPS
• High Dynamic Performance:
– 80-dBc SFDR at 170 MHz
– 71.7-dBFS SNR at 170 MHz
• Crosstalk: > 90 dB at 185 MHz
• Programmable Gain up to 6 dB for
SNR/SFDR Trade-off
• DC Offset Correction
• Output Interface Options:
– 1.8-V Parallel CMOS Interface
– Double Data Rate (DDR) LVDS with
Programmable Swing:
– Standard Swing: 350 mV
– Low Swing: 200 mV
• Supports Low Input Clock Amplitude
Down to 200 mVPP
• Package: 9-mm × 9-mm, 64-Pin VQFN Package
2 Applications
• Wireless Communications Infrastructure
• Software Defined Radios
• Power Amplifier Linearization
3 Description
The ADS4249 is a member of the ADS42xx ultralow-
power family of dual-channel, 12-bit and 14-bit
analog-to-digital converters (ADCs). Innovative
design techniques are used to achieve high dynamic
performance and consume extremely low power with
a 1.8-V supply. This topology makes the ADS4249
well-suited for multi-carrier, wide-bandwidth
communications applications.
The ADS4249 has gain options that can be used to
improve SFDR performance at lower full-scale input
ranges. This device also includes a dc offset
correction loop that can be used to cancel the ADC
offset. Both DDR LVDS and parallel CMOS digital
output interfaces are available in a compact VQFN-64
PowerPAD™ package.
The device includes internal references and the
traditional reference pins and associated decoupling
capacitors have been eliminated. The ADS4249 is
specified over the industrial temperature range
(–40°C to 85°C).
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ADS4249
VQFN (64)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
ADS4249
ADS4249 Block Diagram
INP_A
INM_A
Sampling
Circuit
14-bit ADC
CLKP
CLKM
INP_B
INM_B
Sampling
Circuit
CLK
Gen
14-bit ADC
LVDS
DA0P
DA0M
DA12P
DA12M
CLKOUTP
CLKOUTM
DB0P
DB0M
DB12P
DB12M
VCM
Reference
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



ADS4249
ADS4249
SBAS534E – JULY 2011 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 ADS424x, ADS422x Family Comparison ............. 4
6 Pin Configuration and Functions ......................... 5
7 Specifications....................................................... 10
7.1 Absolute Maximum Ratings .................................... 10
7.2 ESD Ratings............................................................ 10
7.3 Recommended Operating Conditions..................... 11
7.4 Thermal Information ................................................ 11
7.5 Electrical Characteristics: ADS4249 (250 MSPS)... 12
7.6 Electrical Characteristics: General .......................... 13
7.7 Digital Characteristics ............................................. 14
7.8 LVDS and CMOS Modes Timing Requirements..... 15
7.9 LVDS Timings at Lower Sampling Frequencies ..... 16
7.10 CMOS Timings at Lower Sampling Frequencies .. 16
7.11 Serial Interface Timing Characteristics ................. 16
7.12 Reset Timing (Only when Serial Interface is
Used)........................................................................ 17
7.13 Typical Characteristics .......................................... 21
8 Detailed Description ............................................ 28
8.1 Overview ................................................................. 28
8.2 Functional Block Diagram ....................................... 28
8.3 Feature Description................................................. 29
8.4 Device Functional Modes........................................ 31
8.5 Programming........................................................... 37
8.6 Register Maps ......................................................... 41
9 Application and Implementation ........................ 54
9.1 Application Information............................................ 54
9.2 Typical Application ................................................. 60
10 Power Supply Recommendations ..................... 62
10.1 Sharing DRVDD and AVDD Supplies ................... 62
10.2 Using DC-DC Power Supplies .............................. 62
10.3 Power Supply Bypassing ...................................... 62
11 Layout................................................................... 62
11.1 Layout Guidelines ................................................. 62
11.2 Layout Example .................................................... 63
12 Device and Documentation Support ................. 64
12.1 Device Support...................................................... 64
12.2 Documentation Support ........................................ 65
12.3 Community Resources.......................................... 66
12.4 Trademarks ........................................................... 66
12.5 Electrostatic Discharge Caution ............................ 66
12.6 Glossary ................................................................ 66
13 Mechanical, Packaging, and Orderable
Information ........................................................... 66
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (May 2015) to Revision E
Page
• Changed Pin Functions (LVDS Mode) table to comply with RGC Package (LVDS Mode) pin out diagram ......................... 5
• Changed Pin Functions (CMOS Mode) table to comply with RGC Package (CMOS Mode) pin out diagram ..................... 8
• Changed unit in last row of Clock Input, Input clock amplitude differential parameter to VPP in Recommended
Operating Conditions table ................................................................................................................................................... 11
• Added text reference for Table 5 ......................................................................................................................................... 37
Changes from Revision C (July 2012) to Revision D
Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision B (September 2011) to Revision C
Page
• Changed footnote 1 in CMOS Timings at Lower Sampling Frequencies............................................................................. 16
• Changed conditions for ADS4249 Typical Characteristics section ...................................................................................... 21
• Changed register D5h bit names of bits D7, D4, D3, and D0 in Table 10 ........................................................................... 41
• Changed register address D8 to DB in Table 10 ................................................................................................................. 41
• Changed register address D5h to match change in Table 10.............................................................................................. 53
• Changed register address DB to match change in Table 10 ............................................................................................... 53
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