Ultralow-Power ADC. ADS4245-EP Datasheet

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ADS4245-EP Datasheet
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Part ADS4245-EP
Description Ultralow-Power ADC
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ADS4245-EP
SBAS653A – APRIL 2014 – REVISED SEPTEMBER 2018
ADS4245-EP Dual-Channel, 14-Bit, 125MSPS Ultralow-Power ADC
1 Features
1 Ultralow Power with Single 1.8V Supply,
CMOS Output:
– 277mW total power at 125MSPS
• High Dynamic Performance:
– 88dBc SFDR at 170MHz
– 71.4dBFS SNR at 170MHz
• Crosstalk: > 90dB at 185MHz
• Programmable Gain up to 6dB for
SNR/SFDR Trade-off
• DC Offset Correction
• Output Interface Options:
– 1.8V parallel CMOS interface
– Double data rate (DDR) LVDS with
programmable swing:
– Standard swing: 350mV
– Low swing: 200mV
• Supports Low Input Clock Amplitude
Down to 200mVPP
• Supports Defense, Aerospace, and Medical
Applications
– Controlled Baseline
– One Assembly and Test Site
– One Fabrication Site
– Available in Military (–55°C to 125°C)
Temperature Range
– Extended Product Life Cycle
– Extended Product-Change Notification
– Product Traceability
2 Applications
• Wireless Communications Infrastructure
• Software Defined Radio
• Power Amplifier Linearization
3 Description
The ADS4245 is a low-speed variant of the ADS42xx
ultralow-power family of dual-channel, 14-bit analog-
to-digital converters (ADCs). Innovative design
techniques are used to achieve high-dynamic
performance, while consuming extremely low power
with 1.8V supply. This topology makes the ADS4245
well-suited for multi-carrier, wide-bandwidth
communications applications.
The ADS4245 has gain options that can be used to
improve SFDR performance at lower full-scale input
ranges. These device includes a dc offset correction
loop that can be used to cancel the ADC offset. Both
DDR (double data rate) LVDS and parallel CMOS
digital output interfaces are available in a compact
VQFN-64 PowerPAD™ package.
The device includes internal references while the
traditional reference pins and associated decoupling
capacitors have been eliminated. The ADS4245 is
specified over the military temperature range (–55°C
to 125°C).
Device Information
ORDER NUMBER
PACKAGE
BODY SIZE
ADS4245MRGC25EP VQFN (64)
9mm × 9mm
INP_A
INM_A
CLKP
CLKM
INP_B
INM_B
VCM
ADS424x
Block Diagram
AVDD AGND
Sampling
Circuit
14-Bit
ADC
Digital and
DDR
Serializer
CLOCKGEN
Sampling
Circuit
14-Bit
ADC
Digital and
DDR
Serializer
Reference
Control
Interface
DRVDD DRGND
LVDS Interface
Output
Clock Buffer
DA0P
DA0M
DA2P
DA2M
DA4P
DA4M
DA6P
DA6M
DA8P
DA8M
DA10P
DA10M
DA12P
DA12M
CLKOUTP
CLKOUTM
DB0P
DB0M
DB2P
DB2M
DB4P
DB4M
DB6P
DB6M
DB8P
DB8M
DB10P
DB10M
DB12P
DB12M
SDOUT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



Texas Instruments ADS4245-EP
ADS4245-EP
SBAS653A – APRIL 2014 – REVISED SEPTEMBER 2018
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 7
6.1 Absolute Maximum Ratings ...................................... 7
6.2 ESD Ratings.............................................................. 7
6.3 Recommended Operating Conditions....................... 8
6.4 Thermal Information .................................................. 8
6.5 Electrical Characteristics:.......................................... 9
6.6 Electrical Characteristics: General .......................... 10
6.7 Digital Characteristics ............................................. 11
6.8 Timing Characteristics: LVDS And CMOS Modes. 13
6.9 Typical Characteristics: ........................................... 17
6.10 Typical Characteristics: General ........................... 22
6.11 Typical Characteristics: Contour ........................... 23
7 Detailed Description ............................................ 24
7.1 Overview ................................................................. 24
7.2 Functional Block Diagram ....................................... 24
7.3 Feature Description................................................. 25
7.4 Device Functional Modes........................................ 25
7.5 Device Configuration............................................... 32
7.6 Serial Register Map ................................................ 37
7.7 Description Of Serial Registers............................... 38
8 Application and Implementation ........................ 46
8.1 Application Information............................................ 46
8.2 Typical Applications ................................................ 47
9 Power Supply Recommendations...................... 51
10 Layout................................................................... 51
10.1 Layout Guidelines ................................................. 51
10.2 Layout Example .................................................... 52
11 Device and Documentation Support ................. 53
11.1 Device Support .................................................... 53
11.2 Receiving Notification of Documentation Updates 54
11.3 Community Resources.......................................... 55
11.4 Trademarks ........................................................... 55
11.5 Electrostatic Discharge Caution ............................ 55
11.6 Glossary ................................................................ 55
12 Mechanical, Packaging, and Orderable
Information ........................................................... 55
4 Revision History
Changes from Original (April 2014) to Revision A
Page
• Changed Handling Rating To: ESD Ratings ......................................................................................................................... 7
• Moved Storage temperature, Tstg From the ESD Ratings table to the Absolute Maximum Ratings table ............................. 7
• Added a MIN value of 1 MSPS to Low-speed mode enabled in the Recommended Operating Conditions ........................ 8
• Added NOTE to the Application and Implementation........................................................................................................... 46
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Product Folder Links: ADS4245-EP



Texas Instruments ADS4245-EP
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5 Pin Configuration and Functions
ADS4245-EP
SBAS653A – APRIL 2014 – REVISED SEPTEMBER 2018
RGC Package (LVDS Mode) (1)
VQFN-64
(Top View)
DRVDD
DB4M
DB4P
DB6M
DB6P
DB8M
DB8P
DB10M
DB10P
DB12M
DB12P
RESET
SCLK
SDATA
SEN
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Thermal
Pad
48 DRVDD
47 DA6P
46 DA6M
45 DA4P
44 DA4M
43 DA2P
42 DA2M
41 DA0P
40 DA0M
39 NC
38 NC
37 CTRL3
36 CTRL2
35 CTRL1
34 AVDD
33 AVDD
(1) The PowerPAD™ is connected to DRGND.
NOTE: NC = do not connect; must float.
Not to scale
NO.
1, 48
12
NAME
DRVDD
RESET
13
14
15
16, 22, 33, 34
17, 18, 21,
24, 27, 28,
31, 32
19
SCLK
SDATA
SEN
AVDD
AGND
INP_B
# OF PINS
2
1
1
1
1
4
Pin Functions: LVDS Mode
FUNCTION
DESCRIPTION
Input
Output buffer supply
Input
Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized through a
hardware RESET by applying a high pulse on this terminal or by using the software
reset option; refer to the Serial Interface Configuration section.
In parallel interface mode, the RESET terminal must be permanently tied high. SCLK
and SEN are used as parallel control terminals in this mode. This terminal has an
internal 150kΩ pull-down resistor.
Input
This terminal functions as a serial interface clock input when RESET is low. It controls
the low-speed mode selection when RESET is tied high; see Table 9 for detailed
information. This terminal has an internal 150kΩ pull-down resistor.
Input
Serial interface data input; this terminal has an internal 150kΩ pull-down resistor.
Input
This terminal functions as a serial interface enable input when RESET is low. It controls
the output interface and data format selection when RESET is tied high; see Table 10
for detailed information. This terminal has an internal 150kΩ pull-up resistor to AVDD.
Input
Analog power supply
8
Input
Analog ground
1
Input
Differential analog positive input, channel B
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: ADS4245-EP
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