Ultralow-Power ADC. ADS42B49 Datasheet

ADS42B49 ADC. Datasheet pdf. Equivalent

Part ADS42B49
Description Ultralow-Power ADC
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ADS42B49
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ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
ADS42B49 Dual-Channel, 14-Bit, 250-MSPS Ultralow-Power ADC with Analog Input Buffer
1 Features
1 Maximum Sample Rate: 250 MSPS
• Ultralow Power:
– 850-mW Total Power at 250 MSPS
• Integrated Analog Input Buffer:
– Input Capacitance: 2.2 pF at 170 MHz
– Input Resistance: 1.1 kΩ at 170 MHz
• High Dynamic Performance:
– 85-dBc SFDR at 170 MHz
– 70.7-dBFS SNR at 170 MHz
• Crosstalk: > 85 dB at 185 MHz
• Programmable Gain Up to 6 dB for
SNR and SFDR Trade-off
• DC Offset Correction
• Output Interface Options:
– 1.8-V Parallel CMOS Interface
– Double Data Rate (DDR) LVDS with
Programmable Swing:
– Standard Swing: 350 mV
– Low Swing: 200 mV
• Supports Low Input Clock Amplitude
Down to 200 mVPP
• Package: 9.00 mm × 9.00 mm, 64-Pin Quad Flat
No-Lead (VQFN) Package
2 Applications
• Wireless Communications Infrastructure
• Software-Defined Radio
• Power Amplifier Linearization
3 Description
The ADS42B49 is an ultralow-power dual-channel,
14-bit analog-to-digital converter (ADC) featuring
integrated analog input buffers. It uses innovative
design techniques to achieve high dynamic
performance, while consuming extremely low power.
The presence of analog input buffers makes this
device easy to drive and helps achieve high
performance over a wide frequency range. The
ADS42B49 is well-suited for multi-carrier, wide
bandwidth communications applications.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ADS42B49
VQFN(64)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
INP_A
INM_A
CLKP
CLKM
INP_B
INM_B
VCM
SAMPLING
CIRCUIT
LVDS INTERFACE
14-Bit
ADC
DIGITAL
and
DDR SERIALIZER
CLOCKGEN
OUTPUT
CLOCK
BUFFER
SAMPLING
CIRCUIT
14-Bit
ADC
DIGITAL
and
DDR SERIALIZER
ADS42B49
REFERENCE
CONTROL
INTERFACE
DA0P/M
DA2P/M
DA4P/M
DA6P/M
DA8P/M
DA10P/M
DA12P/M
CLKOUTP/M
DB0P/M
DB2P/M
DB4P/M
DB6P/M
DB8P/M
DB10P/M
DB12P/M
SDOUT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



ADS42B49
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Description (continued)......................................... 4
6 ADS424x and ADS422x Family Comparison....... 4
7 Pin Configuration and Functions ......................... 5
8 Specifications......................................................... 8
8.1 Absolute Maximum Ratings ...................................... 8
8.2 ESD Ratings.............................................................. 9
8.3 Recommended Operating Conditions....................... 9
8.4 Thermal Information .................................................. 9
8.5 Electrical Characteristics: ADS42B49 (250 MSPS) 10
8.6 Electrical Characteristics: General .......................... 11
8.7 Digital Characteristics ............................................. 12
8.8 Timing Requirements: LVDS and CMOS Modes.... 13
8.9 Serial Interface Timing Characteristics ................... 14
8.10 Reset Timing (Only When Serial Interface is
Used)........................................................................ 14
8.11 LVDS Timings at Lower Sampling Frequencies ... 14
8.12 CMOS Timings at Lower Sampling Frequencies .. 14
8.13 Typical Characteristics .......................................... 15
9 Parameter Measurement Information ................ 21
10 Detailed Description ........................................... 24
10.1 Overview ............................................................... 24
10.2 Functional Block Diagram ..................................... 24
10.3 Feature Description............................................... 25
10.4 Device Functional Modes...................................... 27
10.5 Programming ........................................................ 33
10.6 Register Maps ...................................................... 36
11 Application and Implementation........................ 49
11.1 Application Information.......................................... 49
11.2 Typical Application ............................................... 52
12 Power Supply Recommendations ..................... 54
12.1 Using DC/DC Power Supplies .............................. 54
12.2 Power Supply Bypassing ...................................... 54
13 Layout................................................................... 55
13.1 Layout Guidelines ................................................. 55
13.2 Layout Example .................................................... 56
14 Device and Documentation Support ................. 57
14.1 Device Support...................................................... 57
14.2 Documentation Support ....................................... 58
14.3 Community Resources.......................................... 59
14.4 Trademarks ........................................................... 59
14.5 Electrostatic Discharge Caution ............................ 59
14.6 Glossary ................................................................ 59
15 Mechanical, Packaging, and Orderable
Information ........................................................... 59
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2013) to Revision C
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Revision A (December 2012) to Revision B
Page
• Changed footnote for CMOS Timings at Lower Sampling Frequencies .............................................................................. 14
• Changed first two sentences in Description of High-Performance Modes table .................................................................. 27
• Changed D2 and D1 bit names in address 03h of Table 10 ................................................................................................ 36
• Changed Register Address 03h ........................................................................................................................................... 38
Changes from Original (December 2012) to Revision A
Page
• Changed product status from Product Preview to Production Data....................................................................................... 1
• Changed Analog Inputs, VID parameter nominal specification in Recommended Operating Conditions table ...................... 9
• Changed Analog Inputs, Maximum analog input frequency parameter rows in Recommended Operating conditions table 9
• Changed footnote 1 in Recommended Operating Conditions table ....................................................................................... 9
• Changed PSRR parameter test conditions in Electrical Characteristics: ADS42B49 table ................................................. 11
• Deleted DNL and INL rows from Electrical Characteristics: ADS42B49 table ..................................................................... 11
• Changed Analog Inputs, VID parameter typical specification in Electrical Characteristics: General table ........................... 11
• Deleted Analog Inputs, Analog input common-mode current row from Electrical Characteristics: General table ............... 11
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