Analog-to-Digital Converter. ADS42JB46 Datasheet

ADS42JB46 Converter. Datasheet pdf. Equivalent

ADS42JB46 Datasheet
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Part ADS42JB46
Description Analog-to-Digital Converter
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ADS42JB46
SBAS621B – JULY 2013 – REVISED SEPTEMBER 2015
ADS42JB46 Dual-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter
1 Features
1 Dual-Channel ADCs
• 14-Bit Resolution
• Maximum Clock Rate: 160 MSPS
• JESD204B Serial Interface
– Subclass 0, 1, 2 Compliant
– Up to 3.125 Gbps
– Two- and Four-Lane Support
• Analog Input Buffer with High-Impedance Input
• Flexible Input Clock Buffer:
Divide-by-1, -2, and -4
• Differential Full-Scale Input: 2 VPP and 2.5 VPP
(Register Programmable)
• Package: 9-mm × 9-mm QFN-64
• Power Dissipation: 679 mW/Ch
• Aperture Jitter: 85 fS rms
• Internal Dither
• Channel Isolation: 100 dB
• Performance:
– fIN = 170 MHz at 2 VPP, –1 dBFS
– SNR: 72.9 dBFS
– SFDR: 90 dBc for HD2, HD3
– SFDR: 100 dBc for Non HD2, HD3
– fIN = 170 MHz at 2.5 VPP, –1 dBFS
– SNR: 74.2 dBFS
– SFDR: 84 dBc for HD2, HD3 and
95 dBc for Non HD2, HD3
Simplified Schematic
INAP,
INAM
CLKINP,
CLKINM
SYSREFP,
SYSREFM
INBP,
INBM
VCM
Device
14-, 16-Bit
ADC
Digital
Block
Gain
Test Modes
JESD204B
Digital
Divide
by 1, 2, 4
PLL
x10, x20
Delay
Common
Mode
14-, 16-Bit
ADC
Digital
Block
Gain
Test Modes
JESD204B
Digital
Device Configuration
OVRA
DA0P,
DA0M
DA1P,
DA1M
SYNC~P,
SYNC~M
DB0P,
DB0M
DB1P,
DB1M
OVRB
2 Applications
• Communication and Cable Infrastructure
• Multi-Carrier, Multimode Cellular Receivers
• Radar and Smart Antenna Arrays
• Broadband Wireless
• Test and Measurement Systems
• Software-Defined and Diversity Radios
• Microwave and Dual-Channel I/Q Receivers
• Repeaters
• Power Amplifier Linearization
3 Description
The ADS42JB46 is a high-linearity, dual-channel, 14-
bit, 160-MSPS, analog-to-digital converter (ADC).
This device supports the JESD204B serial interface
with data rates up to 3.125 Gbps. The buffered
analog input provides uniform input impedance
across a wide frequency range while minimizing
sample-and-hold glitch energy, thus making driving
analog inputs up to very high input frequencies easy.
A sampling clock divider allows more flexibility for
system clock architecture design. The device
employs internal dither algorithms to provide excellent
spurious-free dynamic range (SFDR) over a large
input frequency range.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ADS42JB46
VQFN (64)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
FFT for 170-MHz Input Signal Sampled at 160
MSPS
0
FIN = 170 MHz
SFDR = 92 dBc
SNR = 73 dBFS
−20 SINAD = 72.9 dBFS
THD = 91 dBc
SFDR Non HD2, HD3
−40 = 100 dBc
−60
−80
−100
−120
0
20 40 60
Frequency (MHz)
80
G002
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



Texas Instruments ADS42JB46
ADS42JB46
SBAS621B – JULY 2013 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 3
6 Pin Configuration and Functions ......................... 3
7 Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information .................................................. 6
7.5 Electrical Characteristics: ADS42JB46 ..................... 7
7.6 Electrical Characteristics: General ............................ 8
7.7 Timing Characteristics............................................... 9
7.8 Digital Characteristics ............................................. 10
7.9 Reset Timing .......................................................... 10
7.10 Serial Interface Timing .......................................... 11
7.11 Typical Characteristics: ADS42JB46 .................... 14
7.12 Typical Characteristics: Contour ........................... 20
8 Detailed Description ............................................ 22
8.1 Overview ................................................................. 22
8.2 Functional Block Diagram ....................................... 22
8.3 Feature Description................................................. 23
8.4 Device Functional Modes........................................ 24
8.5 Programming........................................................... 31
8.6 Register Maps ......................................................... 34
9 Application and Implementation ........................ 47
9.1 Application Information............................................ 47
9.2 Typical Application .................................................. 47
10 Power Supply Recommendations ..................... 53
11 Layout................................................................... 53
11.1 Layout Guidelines ................................................. 53
11.2 Layout Example .................................................... 54
12 Device and Documentation Support ................. 55
12.1 Device Support...................................................... 55
12.2 Community Resources.......................................... 55
12.3 Trademarks ........................................................... 55
12.4 Electrostatic Discharge Caution ............................ 55
12.5 Glossary ................................................................ 55
13 Mechanical, Packaging, and Orderable
Information ........................................................... 55
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (August 2013) to Revision B
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Original (July 2013) to Revision A
Page
• Changed document status to Production Data; moved from 1-page Preview ....................................................................... 1
2 Submit Documentation Feedback
Product Folder Links: ADS42JB46
Copyright © 2013–2015, Texas Instruments Incorporated



Texas Instruments ADS42JB46
www.ti.com
5 Device Comparison Table
INTERFACE OPTION
DDR, QDR LVDS
JESD204B
14-BIT,
160 MSPS
ADS42JB46
ADS42JB46
SBAS621B – JULY 2013 – REVISED SEPTEMBER 2015
14-BIT,
250 MSPS
ADS42LB49
ADS42JB46
16-BIT,
250 MSPS
ADS42LB69
ADS42JB69
6 Pin Configuration and Functions
RGC Package
64-Pin VQFN
Top View
DGND 1
DRVDD 2
DGND 3
MODE 4
STBY 5
PDN_GBL 6
DRVDD 7
SYNC~M 8
SYNC~P 9
CTRL2 10
AVDD 11
AGND 12
INBP 13
INBM 14
AGND 15
AVDD 16
Thermal Pad
48 DGND
47 DRVDD
46 DGND
45 SDOUT
44 RESET
43 SCLK
42 SDATA
41 SEN
40 AVDD
39 CTRL1
38 AVDD
37 AGND
36 INAP
35 INAM
34 AGND
33 AVDD
Copyright © 2013–2015, Texas Instruments Incorporated
Product Folder Links: ADS42JB46
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