Document
Product Folder
Sample & Buy
Technical Documents
Tools & Software
Support & Community
ADS42JB46
SBAS621B – JULY 2013 – REVISED SEPTEMBER 2015
ADS42JB46 Dual-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter
1 Features
•1 Dual-Channel ADCs • 14-Bit Resolution • Maximum Clock Rate: 160 MSPS • JESD204B Serial Interface
– Subclass 0, 1, 2 Compliant – Up to 3.125 Gbps – Two- and Four-Lane Support • Analog Input Buffer with High-Impedance Input • Flexible Input Clock Buffer: Divide-by-1, -2, and -4 • Differential Full-Scale Input: 2 VPP and 2.5 VPP (Register Programmable) • Package: 9-mm × 9-mm QFN-64 • Power Dissipation: 679 mW/Ch • Aperture Jitter: 85 fS rms • Internal Dither • Channel Isolation: 100 dB • Performance: – fIN = 170 MHz at 2 VPP, –1 dBFS
– SNR: 72.9 dBFS – SFDR: 90 dBc for HD2, HD3 – SFDR: 100 dBc for Non HD2, HD3 – fIN = 170 MHz at 2.5 VPP, –1 dBFS – SNR: 74.2 dBFS – SFDR: 84 dBc for HD2, HD3 and
95 dBc for Non HD2, HD3
Simplified Schematic
INAP, INAM
CLKINP, CLKINM SYSREFP, SYSREFM
INBP, INBM
VCM
Device
14-, 16-Bit ADC
Digital Block
Gain Test Modes
JESD204B Digital
Divide by 1, 2, 4
PLL x10, x20
Delay
Common Mode
14-, 16-Bit ADC
Digital Block
Gain Test Modes
JESD204B Digital
Device Configuration
OVRA DA0P, DA0M DA1P, DA1M
SYNC~P, SYNC~M
DB0P, DB0M DB1P, DB1M OVRB
2 Applications
• Communication and Cable Infrastructure • Multi-Carrier, Multimode Cellular Receivers • Radar and Smart Antenna Arrays • Broadband Wireless • Test and Measurement Systems • Software-Defined and Diversity Radios • Microwave and Dual-Channel I/Q Receivers • Repeaters • Power Amplifier Linearization
3 Description
The ADS42JB46 is a high-linearity, dual-channel, 14bit, 160-MSPS, analog-to-digital converter (ADC). This device supports the JESD204B serial interface with data rates up to 3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy, thus making driving analog inputs up to very high input frequencies easy. A sampling clock divider allows more flexibility for system clock architecture design. The device employs internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ADS42JB46
VQFN (64)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
FFT for 170-MHz Input Signal Sampled at 160 MSPS
0 FIN = 170 MHz SFDR = 92 dBc SNR = 73 dBFS
−20 SINAD = 72.9 dBFS THD = 91 dBc SFDR Non HD2, HD3
−40 = 100 dBc
−60
−80
−100
RESET SEN
SCLK SDATA SDOUT
PDN PDN_GBL
MODE CTRL1 CTRL2 STBY
Amplitude (dBFS)
−120 0
20 40 60 Frequency (MHz)
80
G002
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS42JB46
SBAS621B – JULY 2013 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1 Features .................................................................. 1 2 Applications ........................................................... 1 3 Description ............................................................. 1 4 Revision History..................................................... 2 5 Device Comparison Table..................................... 3 6 Pin Configuration and Functions ......................... 3 7 Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5 7.2 ESD Ratings.............................................................. 5 7.3 Recommended Operating Conditions....................... 6 7.4 Thermal Information .................................................. 6 7.5 Electrical Characteristics: ADS42JB46 ..................... 7 7.6 Electrical Characteristics: General ............................ 8 7.7 Timing Characteristics............................................... 9 7.8 Digital Characteristics ............................................. 10 7.9 Reset Timing .......................................................... 10 7.10 Serial Interface Timing .......................................... 11 7.11 Typical Characteristics: ADS42JB46 .................... 14 7.12 Typical Characteristics: Contour ........................... 20 8 Detailed Description ............................................ 22
8.1 Overview ................................................................. 22 8.2 Functional Block Diagram ....................................... 22 8.3 Feature Description................................................. 23 8.4 Device Functional Modes........................................ 24 8.5 Programming........................................................... 31 8.6 Register Map.