Analog-to-Digital Converter. ADS42JB49 Datasheet

ADS42JB49 Converter. Datasheet pdf. Equivalent

ADS42JB49 Datasheet
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Part ADS42JB49
Description Analog-to-Digital Converter
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ADS42JB49, ADS42JB69
SLAS900F – OCTOBER 2012 – REVISED DECEMBER 2014
ADS42JBx9 Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters
1 Features
1 Dual-Channel ADCs
• 14- and 16-Bit Resolution
• Maximum Clock Rate: 250 MSPS
• JESD204B Serial Interface
– Subclass 0, 1, 2 Compliant
– Up to 3.125 Gbps
– Two and Four Lanes Support
• Analog Input Buffer with High-Impedance Input
• Flexible Input Clock Buffer:
Divide-by-1, -2, and -4
• Differential Full-Scale Input: 2 VPP and 2.5 VPP
(Register Programmable)
• Package: 9-mm × 9-mm VQFN-64
• Power Dissipation: 850 mW/Ch
• Aperture Jitter: 85 fS rms
• Internal Dither
• Channel Isolation: 100 dB
• Performance:
– fIN = 170 MHz at 2 VPP, –1 dBFS
– SNR: 73.3 dBFS
– SFDR: 93 dBc for HD2, HD3
– SFDR: 100 dBc for Non HD2, HD3
– fIN = 170 MHz at 2.5 VPP, –1 dBFS
– SNR: 74.7 dBFS
– SFDR: 89 dBc for HD2, HD3 and
95 dBc for Non HD2, HD3
2 Applications
• Communication and Cable Infrastructure
• Multi-Carrier, Multimode Cellular Receivers
• Radar and Smart Antenna Arrays
• Broadband Wireless
• Test and Measurement Systems
• Software-Defined and Diversity Radios
• Microwave and Dual-Channel I/Q Receivers
• Repeaters
• Power Amplifier Linearization
3 Description
The ADS42JB69 and ADS42JB49 are high-linearity,
dual-channel, 16- and 14-bit, 250-MSPS, analog-to-
digital converters (ADCs). These devices support the
JESD204B serial interface with data rates up to
3.125 Gbps. The buffered analog input provides
uniform input impedance across a wide frequency
range while minimizing sample-and-hold glitch energy
making it easy to drive analog inputs up to very high
input frequencies. A sampling clock divider allows
more flexibility for system clock architecture design.
The devices employ internal dither algorithms to
provide excellent spurious-free dynamic range
(SFDR) over a large input frequency range.
Device Information(1)
PART NUMBER PACKAGE
INTERFACE OPTION
ADS42JB49
VQFN (64)
14-bit DDR or QDR LVDS
14-bit JESD204B
ADS42JB69
VQFN (64)
16-bit DDR or QDR LVDS
16-bit JESD204B
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
space
space
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



Texas Instruments ADS42JB49
ADS42JB49, ADS42JB69
SLAS900F – OCTOBER 2012 – REVISED DECEMBER 2014
INAP,
INAM
CLKINP,
CLKINM
SYSREFP,
SYSREFM
INBP,
INBM
VCM
Simplified Schematic
Device
14-, 16-Bit
ADC
Digital
Block
Gain
Test Modes
JESD204B
Digital
Divide
by 1, 2, 4
PLL
x10, x20
Delay
Common
Mode
14-, 16-Bit
ADC
Digital
Block
Gain
Test Modes
JESD204B
Digital
Device Configuration
OVRA
DA0P,
DA0M
DA1P,
DA1M
SYNC~P,
SYNC~M
DB0P,
DB0M
DB1P,
DB1M
OVRB
www.ti.com
FFT for 170MHz Input Signal
0
Fs = 250Msps
Fin = 170MHz
-20 Ain = -1dBFS
HD2 = 90dBc
HD3 = 89dBc
-40 Non HD2,3 = 100dBc
-60
-80
-100
-120
0
25 50 75
Frequency (MHz)
100
125
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Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: ADS42JB49 ADS42JB69



Texas Instruments ADS42JB49
www.ti.com
ADS42JB49, ADS42JB69
SLAS900F – OCTOBER 2012 – REVISED DECEMBER 2014
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 3
5 Device Comparison Table..................................... 5
6 Pin Configuration and Functions ......................... 5
7 Specifications......................................................... 7
7.1 Absolute Maximum Ratings ...................................... 7
7.2 ESD Ratings.............................................................. 7
7.3 Recommended Operating Conditions....................... 8
7.4 Thermal Information .................................................. 8
7.5 Electrical Characteristics: ADS42JB69 (16-Bit) ........ 9
7.6 Electrical Characteristics: ADS42JB49 (14-Bit) ...... 10
7.7 Electrical Characteristics: General .......................... 11
7.8 Digital Characteristics ............................................. 12
7.9 Timing Characteristics............................................. 13
7.10 Typical Characteristics: ADS42JB69 .................... 15
7.11 Typical Characteristics: ADS42JB49 .................... 20
7.12 Typical Characteristics: Common ......................... 25
7.13 Typical Characteristics: Contour ........................... 26
8 Parameter Measurement Information ................ 29
9 Detailed Description ............................................ 31
9.1 Overview ................................................................. 31
9.2 Functional Block Diagram ....................................... 31
9.3 Feature Description................................................. 31
9.4 Device Functional Modes........................................ 33
9.5 Programming........................................................... 39
9.6 Register Maps ......................................................... 42
10 Application and Implementation........................ 57
10.1 Application Information.......................................... 57
10.2 Typical Application ................................................ 57
11 Power Supply Recommendations ..................... 63
12 Layout................................................................... 63
12.1 Layout Guidelines ................................................. 63
12.2 Layout Example .................................................... 65
13 Device and Documentation Support ................. 66
13.1 Device Support...................................................... 66
13.2 Documentation Support ........................................ 68
13.3 Related Links ........................................................ 68
13.4 Trademarks ........................................................... 68
13.5 Electrostatic Discharge Caution ............................ 68
13.6 Glossary ................................................................ 68
14 Mechanical, Packaging, and Orderable
Information ........................................................... 68
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (August 2013) to Revision F
Page
• Changed format to meet latest data sheet standards ............................................................................................................ 1
• Added ESD Ratings table and Feature Description, Device Functional Modes, Application and
Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical,
Packaging, and Orderable Information sections..................................................................................................................... 1
• Changed title of Device Comparison Table............................................................................................................................ 5
• Changed title of Pin Functions table....................................................................................................................................... 6
• Deleted Ordering Information table ........................................................................................................................................ 7
• Corrected names of registers 10h, 11h, 12h, and 13h in Table 13 ..................................................................................... 42
Changes from Revision D (August 2013) to Revision E
Page
• Changed document status to Production Data....................................................................................................................... 1
Changes from Revision C (July 2013) to Revision D
Page
• Updated front page block diagram ......................................................................................................................................... 2
• Changed 2-VPP Full-Scale INL maximum specification in ADS42JB49 Electrical Characteristics table .............................. 10
Changes from Revision B (July 2013) to Revision C
Page
• Added Internal Dither in Features Section ............................................................................................................................. 1
• Changed From "The devices provide excellent" to "The devices employ internal dither algorithms to provide" ................... 1
• Changed 2-VPP Full-Scale INL maximum specification in ADS42JB69 Electrical Characteristics table ................................ 9
Copyright © 2012–2014, Texas Instruments Incorporated
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