Analog-to-Digital Converter. ADS42JB69 Datasheet

ADS42JB69 Converter. Datasheet pdf. Equivalent

Part ADS42JB69
Description Analog-to-Digital Converter
Feature Product Folder Sample & Buy Technical Documents Tools & Software Support & Community ADS42JB49,.
Manufacture etcTI
Datasheet
Download ADS42JB69 Datasheet



ADS42JB69
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
ADS42JB49, ADS42JB69
SLAS900F – OCTOBER 2012 – REVISED DECEMBER 2014
ADS42JBx9 Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters
1 Features
1 Dual-Channel ADCs
• 14- and 16-Bit Resolution
• Maximum Clock Rate: 250 MSPS
• JESD204B Serial Interface
– Subclass 0, 1, 2 Compliant
– Up to 3.125 Gbps
– Two and Four Lanes Support
• Analog Input Buffer with High-Impedance Input
• Flexible Input Clock Buffer:
Divide-by-1, -2, and -4
• Differential Full-Scale Input: 2 VPP and 2.5 VPP
(Register Programmable)
• Package: 9-mm × 9-mm VQFN-64
• Power Dissipation: 850 mW/Ch
• Aperture Jitter: 85 fS rms
• Internal Dither
• Channel Isolation: 100 dB
• Performance:
– fIN = 170 MHz at 2 VPP, –1 dBFS
– SNR: 73.3 dBFS
– SFDR: 93 dBc for HD2, HD3
– SFDR: 100 dBc for Non HD2, HD3
– fIN = 170 MHz at 2.5 VPP, –1 dBFS
– SNR: 74.7 dBFS
– SFDR: 89 dBc for HD2, HD3 and
95 dBc for Non HD2, HD3
2 Applications
• Communication and Cable Infrastructure
• Multi-Carrier, Multimode Cellular Receivers
• Radar and Smart Antenna Arrays
• Broadband Wireless
• Test and Measurement Systems
• Software-Defined and Diversity Radios
• Microwave and Dual-Channel I/Q Receivers
• Repeaters
• Power Amplifier Linearization
3 Description
The ADS42JB69 and ADS42JB49 are high-linearity,
dual-channel, 16- and 14-bit, 250-MSPS, analog-to-
digital converters (ADCs). These devices support the
JESD204B serial interface with data rates up to
3.125 Gbps. The buffered analog input provides
uniform input impedance across a wide frequency
range while minimizing sample-and-hold glitch energy
making it easy to drive analog inputs up to very high
input frequencies. A sampling clock divider allows
more flexibility for system clock architecture design.
The devices employ internal dither algorithms to
provide excellent spurious-free dynamic range
(SFDR) over a large input frequency range.
Device Information(1)
PART NUMBER PACKAGE
INTERFACE OPTION
ADS42JB49
VQFN (64)
14-bit DDR or QDR LVDS
14-bit JESD204B
ADS42JB69
VQFN (64)
16-bit DDR or QDR LVDS
16-bit JESD204B
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
space
space
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



ADS42JB69
ADS42JB49, ADS42JB69
SLAS900F – OCTOBER 2012 – REVISED DECEMBER 2014
INAP,
INAM
CLKINP,
CLKINM
SYSREFP,
SYSREFM
INBP,
INBM
VCM
Simplified Schematic
Device
14-, 16-Bit
ADC
Digital
Block
Gain
Test Modes
JESD204B
Digital
Divide
by 1, 2, 4
PLL
x10, x20
Delay
Common
Mode
14-, 16-Bit
ADC
Digital
Block
Gain
Test Modes
JESD204B
Digital
Device Configuration
OVRA
DA0P,
DA0M
DA1P,
DA1M
SYNC~P,
SYNC~M
DB0P,
DB0M
DB1P,
DB1M
OVRB
www.ti.com
FFT for 170MHz Input Signal
0
Fs = 250Msps
Fin = 170MHz
-20 Ain = -1dBFS
HD2 = 90dBc
HD3 = 89dBc
-40 Non HD2,3 = 100dBc
-60
-80
-100
-120
0
25 50 75
Frequency (MHz)
100
125
2 Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: ADS42JB49 ADS42JB69





@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)