Ultralow-Power ADC. ADS41B25 Datasheet

ADS41B25 ADC. Datasheet pdf. Equivalent

ADS41B25 Datasheet
Recommendation ADS41B25 Datasheet
Part ADS41B25
Description Ultralow-Power ADC
Feature ADS41B25; ADS41B25 www.ti.com 12-Bit, 125MSPS, Ultralow-Power ADC with Analog Buffer Check for Samples: ADS4.
Manufacture etcTI
Datasheet
Download ADS41B25 Datasheet




Texas Instruments ADS41B25
ADS41B25
www.ti.com
12-Bit, 125MSPS, Ultralow-Power ADC with Analog Buffer
Check for Samples: ADS41B25
SBAS548 JUNE 2011
FEATURES
1
23 Resolution: 12-Bit, 125MSPS
Integrated High-Impedance
Analog Input Buffer:
Input Capacitance at dc: 3.5pF
Input Resistance at dc: 10kΩ
Maximum Sample Rate: 125MSPS
Ultralow Power:
1.8V Analog Power: 114mW
3.3V Buffer Power: 96mW
I/O Power: 100mW (DDR LVDS)
High Dynamic Performance:
SNR: 68.3dBFS at 170MHz
SFDR: 87dBc at 170MHz
Output Interface:
Double Data Rate (DDR) LVDS with
Programmable Swing and Strength:
Standard Swing: 350mV
Low Swing: 200mV
Default Strength: 100Ω Termination
2x Strength: 50Ω Termination
1.8V Parallel CMOS Interface Also
Supported
Programmable Gain for SNR/SFDR Trade-Off
DC Offset Correction
Supports Low Input Clock Amplitude
Package: QFN-48 (7mm × 7mm)
DESCRIPTION
The ADS41B25 is a member of the ultralow-power
ADS4xxx analog-to-digital converter (ADC) family,
featuring integrated analog input buffers. This device
uses innovative design techniques to achieve high
dynamic performance, while consuming extremely
low power. The analog input pins have buffers, with
the benefits of constant performance and input
impedance across a wide frequency range. The
device is well-suited for multi-carrier, wide bandwidth
communications applications such as PA
linearization.
The ADS41B25 has features such as digital gain and
offset correction. The gain option can be used to
improve SFDR performance at lower full-scale input
ranges, especially at high input frequencies. The
integrated dc offset correction loop can be used to
estimate and cancel the ADC offset. At lower
sampling rates, the ADC automatically operates at
scaled-down power with no loss in performance.
The device supports both double data rate (DDR)
low-voltage differential signaling (LVDS) and parallel
CMOS digital output interfaces. The low data rate of
the DDR LVDS interface (maximum 500MBPS)
makes it possible to use low-cost field-programmable
gate array (FPGA)-based receivers. The device has a
low-swing LVDS mode that can be used to further
reduce the power consumption. The strength of the
LVDS output buffers can also be increased to support
50Ω differential termination.
The device is available in a compact QFN-48
package and is specified over the industrial
temperature range (40°C to +85°C).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments, Incorporated.
2
All other trademarks are the property of their respective owners.
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated



Texas Instruments ADS41B25
ADS41B25
SBAS548 JUNE 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE- PACKAGE
PRODUCT LEAD
DESIGNATOR
ADS41B25 QFN-48
RGZ
ORDERING INFORMATION(1)
SPECIFIED
TEMPERATURE
RANGE
LEAD/BALL
ECO PLAN(2)
FINISH
40°C to +85°C
GREEN (RoHS,
no Sb/Br)
Cu/NiPdAu
PACKAGE
MARKING
AZ41B25
ORDERING
NUMBER
ADS41B25IRGZR
ADS41B25IRGZT
TRANSPORT
MEDIA
Tape and reel
Tape and reel
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
(2) Eco Plan is the planned eco-friendly classification. Green (RoHS, no Sb/Br): TI defines Green to mean Pb-Free (RoHS compatible) and
free of Bromine- (Br) and Antimony- (Sb) based flame retardants. Refer to the Quality and Lead-Free (Pb-Free) Data web site for more
information.
ABSOLUTE MAXIMUM RATINGS(1)
Supply voltage range, AVDD
Supply voltage range, AVDD_BUF
Supply voltage range, DRVDD
Voltage between AGND and DRGND
Voltage between AVDD to DRVDD (when AVDD leads DRVDD)
Voltage between DRVDD to AVDD (when DRVDD leads AVDD)
Voltage between AVDD_BUF to DRVDD/AVDD
Voltage applied to input pins
INP, INM
CLKP, CLKM(2), RESET, SCLK,
SDATA, SEN, DFS
Operating free-air temperature range, TA
Operating junction temperature range, TJ
Storage temperature range, Tstg
ESD, human body model (HBM)
ADS41B25
MIN MAX
0.3 2.1
0.3 3.9
0.3 2.1
0.3 0.3
2.4 2.4
2.4 2.4
4.2 4.2
0.3
Minimum
(1.9, AVDD + 0.3)
0.3 AVDD + 0.3
40 +85
+125
65 +150
2
UNIT
V
V
V
V
V
V
V
V
V
°C
°C
°C
kV
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is less than |0.3V|.
Doing so prevents the ESD protection diodes at the clock input pins from turning on.
THERMAL INFORMATION
THERMAL METRIC(1)
ADS41B25
RGZ
UNITS
48 PINS
θJA
θJCtop
θJB
ψJT
ψJB
θJCbot
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
27.9
15.1
5.4
°C/W
0.3
5.4
1.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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Product Folder Link(s): ADS41B25
Copyright © 2011, Texas Instruments Incorporated



Texas Instruments ADS41B25
ADS41B25
www.ti.com
SBAS548 JUNE 2011
RECOMMENDED OPERATING CONDITIONS
SUPPLIES
AVDD
Analog supply voltage
AVDD_BUF
Analog buffer supply voltage
DRVDD
Digital supply voltage
ANALOG INPUTS
Differential input voltage range(1)
Input common-mode voltage
Maximum analog input frequency with 1.5VPP input amplitude(2)
Maximum analog input frequency with 1VPP input amplitude(2)
CLOCK INPUT
Low-speed mode enabled(3)
Low-speed mode disabled(3)
Input clock amplitude differential (VCLKP VCLKM)
Sine wave, ac-coupled
LVPECL, ac-coupled
LVDS, ac-coupled
LVCMOS, single-ended, ac-coupled
Input clock duty Low-speed mode enabled
cycle
Low-speed mode disabled
DIGITAL OUTPUTS
CLOAD
RLOAD
Maximum external load capacitance from each output pin to DRGND
Differential load resistance between the LVDS output pairs
(LVDS mode)
TA Operating free-air temperature
ADS41B25
MIN TYP
1.7 1.8
3 3.3
1.7 1.8
1.5
1.7 ± 0.05
400
600
20
80
0.2 1.5
1.6
0.7
1.8
40 50
35 50
5
100
40
MAX
UNIT
1.9 V
3.6 V
1.9 V
VPP
V
MHz
MHz
80 MSPS
125 MSPS
VPP
VPP
VPP
V
60 %
65 %
pF
Ω
+85 °C
(1) With 0dB gain. See the Gain for SFDR/SNR Trade-Off section in Application Information for the relationship between input voltage range
and gain.
(2) See the Theory of Operation section in the Application Information.
(3) See the Serial Interface section for details on the low-speed mode.
PARAMETER
MODE 1
MODE 2
HIGH-PERFORMANCE MODES(1)(2)(3)
DESCRIPTION
Set the MODE 1 register bits to get the best performance across sample clock and input signal frequencies.
Register address = 03h, register data = 03h.
Set the MODE 2 register bit to get the best performance at high input signal frequencies greater than 230MHz.
Register address = 4Ah, register data = 01h.
(1) It is recommended to use these modes to get best performance. These modes can only be set with the serial interface.
(2) See the Serial Interface section for details on register programming.
(3) Note that these modes cannot be set when the serial interface is not used (when the RESET pin is tied high); see the Device
Configuration section.
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): ADS41B25
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