ADS41B25

ADS41B25 www.ti.com 12-Bit, 125MSPS, Ultralow-Power ADC with Analog Buffer Check for Samples: ADS41B25 SBAS548 – JUNE 2011 FEATURES 1 23 Resolution: 12-Bit, 125MSPS Integrated High-Impedance Analog Input Buffer: – Input Capacitance at dc: 3.5pF – Input Resistance at dc: 10kΩ Maximum Sample Rate: 125MSPS Ultralow Power: – 1.8V Analog Power: 114mW – 3.3V Buffer Power: 96mW – I/O Power: 100mW (DDR LVDS) High Dynamic Performance: – SNR: 68.3dBFS at 170MHz – SFDR: 87dBc at 170MHz Output Interface: – Double Data Rate (DDR) LVDS with Programmable Swing and Strength: – Standard Swing: 350mV – Low Swing: 200mV – Default Strength: 100Ω Termination – 2x Strength: 50Ω Termination – 1.8V Parallel CMOS Interface Also Supported Programmable Gain for SNR/SFDR Trade-Off DC Offset Correction Supports Low Input Clock Amplitude Package: QFN-48 (7mm × 7mm) DESCRIPTION The ADS41B25 is a member of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. This device uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power. The analog input pins have buffers, with the benefits of constant performance and input impedance across a wide frequency range. The device is well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization. The ADS41B25 has features such as digital gain and offset correction. The gain option can be used to improve SFDR...