Ultralow-Power ADC. ADS41B49 Datasheet

ADS41B49 ADC. Datasheet pdf. Equivalent

Part ADS41B49
Description Ultralow-Power ADC
Feature Product Folder Sample & Buy Technical Documents Tools & Software Support & Community ADS41B29, .
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ADS41B49
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Buy
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ADS41B29, ADS41B49
SBAS486F – NOVEMBER 2009 – REVISED FEBRUARY 2016
ADS41Bx9 14- and 12-Bit, 250-MSPS, Ultralow-Power ADCs with Analog Buffers
1 Features
1 ADS41B49: 14-Bit, 250 MSPS
ADS41B29: 12-Bit, 250 MSPS
• Integrated High-Impedance
Analog Input Buffer:
– Input Capacitance: 2 pF
– 200-MHz Input Resistance: 3 kΩ
• Maximum Sample Rate: 250 MSPS
• Ultralow Power:
– 1.8-V Analog Power: 180 mW
– 3.3-V Buffer Power: 96 mW
– I/O Power: 135 mW (DDR LVDS)
• High Dynamic Performance:
– SNR: 69 dBFS at 170 MHz
– SFDR: 82.5 dBc at 170 MHz
• Output Interface:
– Double Data Rate (DDR) LVDS with
Programmable Swing and Strength:
– Standard Swing: 350 mV
– Low Swing: 200 mV
– Default Strength: 100-Ω Termination
– 2x Strength: 50-Ω Termination
– 1.8-V Parallel CMOS Interface Also Supported
• Programmable Gain for SNR, SFDR Trade-Off
• DC Offset Correction
• Supports Low Input Clock Amplitude
• Package: VQFN-48 (7 mm × 7 mm)
2 Applications
• Power Amplifier Linearization
• Software Defined Radio
• Wireless Communications Infrastructure
3 Description
The ADS41Bx9 are members of the ultralow-power
ADS4xxx analog-to-digital converter (ADC) family,
featuring integrated analog input buffers. These
devices use innovative design techniques to achieve
high dynamic performance, and consume extremely
low power. The analog input pins have buffers, with
benefits of constant performance and input
impedance across a wide frequency range. The
devices are well-suited for multi-carrier, wide
bandwidth communications applications such as PA
linearization.
The ADS41Bx9 have features such as digital gain
and offset correction. The gain option can be used to
improve SFDR performance at lower full-scale input
ranges, especially at high input frequencies. The
integrated dc offset correction loop can be used to
estimate and cancel the ADC offset. At lower
sampling rates, the ADC automatically operates at
scaled-down power with no loss in performance.
The devices support both double data rate (DDR)
low-voltage differential signaling (LVDS) and parallel
CMOS digital output interfaces. The low data rate of
the DDR LVDS interface (maximum 500 MBPS)
makes using low-cost field-programmable gate array
(FPGA)-based receivers possible. The devices have
a low-swing LVDS mode that can be used to further
reduce the power consumption. The strength of the
LVDS output buffers can also be increased to support
50-Ω differential termination.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ADS41Bx9
VQFN (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
ADS41B49 Block Diagram
AVDD AGND
DRVDD DRGND
DDR LVDS
Interface
CLKP
CLKM
CLOCKGEN
AVDD_BUF
INP
Sampling
Circuit
INM
Analog Buffers
14-Bit
ADC
Common
Digital Functions
VCM
Reference
Control
Interface
DDR
Serializer
ADS41B49
OE
CLKOUTP
CLKOUTM
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
D6_D7_P
D6_D7_M
D8_D9_P
D8_D9_M
D10_D11_P
D10_D11_M
D12_D13_P
D12_D13_M
OVR_SDOUT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



ADS41B49
ADS41B29, ADS41B49
SBAS486F – NOVEMBER 2009 – REVISED FEBRUARY 2016
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 4
6 Specifications......................................................... 7
6.1 Absolute Maximum Ratings ...................................... 7
6.2 ESD Ratings.............................................................. 7
6.3 Recommended Operating Conditions....................... 8
6.4 Thermal Information .................................................. 8
6.5 Electrical Characteristics: General ............................ 9
6.6 Electrical Characteristics: ADS41B29, ADS41B49 . 10
6.7 Digital Characteristics ............................................. 11
6.8 Timing Requirements: LVDS and CMOS Modes.... 12
6.9 Timing Requirements: Reset .................................. 13
6.10 Timing Requirements: LVDS Timing Across
Sampling Frequencies ............................................. 13
6.11 Timing Requirements: CMOS Timing Across
Sampling Frequencies ............................................. 13
6.12 Timing Requirements: CMOS Timing Across
Sampling Frequencies ............................................. 13
6.13 Typical Characteristics: ADS41B49 ...................... 14
6.14 Typical Characteristics: ADS41B29 ...................... 17
6.15 Typical Characteristics: General ........................... 20
6.16 Typical Characteristics: Contour ........................... 21
7 Parameter Measurement Information ................ 22
7.1 Timing Diagrams ..................................................... 22
8 Detailed Description ............................................ 25
8.1 Overview ................................................................. 25
8.2 Functional Block Diagram ....................................... 25
8.3 Feature Description................................................. 26
8.4 Device Functional Modes........................................ 36
8.5 Programming........................................................... 38
8.6 Register Maps ......................................................... 40
9 Application and Implementation ........................ 48
9.1 Application Information............................................ 48
10 Power Supply Recommendations ..................... 50
10.1 Power-Supply Sequence....................................... 50
11 Layout................................................................... 50
11.1 Layout Guidelines ................................................. 50
12 Device and Documentation Support ................. 51
12.1 Documentation Support ........................................ 51
12.2 Related Links ........................................................ 51
12.3 Community Resources.......................................... 51
12.4 Trademarks ........................................................... 51
12.5 Electrostatic Discharge Caution ............................ 51
12.6 Glossary ................................................................ 51
13 Mechanical, Packaging, and Orderable
Information ........................................................... 51
4 Revision History
Changes from Revision E (July 2012) to Revision F
Page
• Changed title and changed ADS41B49/29 to ADS41Bx9 and QFN to VQFN throughout document .................................... 1
• Added Applications section, Device Information table, front-page figure, ESD Ratings table, Feature Description
section, Device Functional Modes section, Programming section, Register Maps section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
• Deleted Ordering Information table ....................................................................................................................................... 1
• Changed Pin Functions table: changed title and format ....................................................................................................... 6
• Added Added last row to Voltage applied to input pins section in Absolute Maximum Ratings table ................................... 7
• Changed Temperature parameters in Absolute Maximum Ratings table: changed format of Temperature section and
changed maximum specifications for TA and TJ ..................................................................................................................... 7
• Changed TYP column header to NOM in Recommended Operating Conditions table ......................................................... 8
• Changed Digital Outputs, TJ parameter in Recommended Operating Conditions table ........................................................ 8
• Deleted High-Performance Modes section from Recommended Operating Conditions table ............................................... 8
• Changed conditions of Electrical Characteristics: General table from temperature to ambient temperature ........................ 9
• Changed conditions of Electrical Characteristics: ADS41B29, ADS41B49 table from temperature to ambient
temperature .......................................................................................................................................................................... 10
• Added footnote 1 to Electrical Characteristics: ADS41B29, ADS41B49 table ..................................................................... 10
• Changed conditions of Timing Requirements: LVDS and CMOS Modes table from temperature to ambient temperature 12
• Added footnotes 6 and 7 to Timing Requirements: LVDS and CMOS Modes table............................................................ 12
• Added footnote 1 to Timing Requirements: Reset table ..................................................................................................... 13
• Changed title of Figure 13 and Figure 14 ............................................................................................................................ 16
• Changed title of Figure 31 and Figure 32 ............................................................................................................................ 19
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