RF Transceiver. AFE7700 Datasheet

AFE7700 Transceiver. Datasheet pdf. Equivalent

Part AFE7700
Description Quad-Channel General Purpose RF Transceiver
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AFE7700
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AFE7700
SLOSE44A – OCTOBER 2019 – REVISED MARCH 2020
AFE7700 Quad-Channel General Purpose RF Transceiver
1 Features
1 Quad transmitters based on direct up-conversion
architecture:
– Up to 600 MHz of RF transmitted bandwidth
per chain
• Quad receivers based on 0-IF down-conversion
architecture:
– Up to 200 MHz of RF received bandwidth per
chain
• Feedback chain based on RF sampling ADC:
– Up to 600 MHz of RF received bandwidth
• RF frequency range: 600 MHz to 6 GHz
• Four wideband fractional-N PLL, VCO for TX and
RX LO
• Dedicated integer-N PLL, VCO for data converters
clock generation
• JESD204B and JESD204C SerDes interface
support:
– 8 SerDes transceivers up to 29.5 Gbps
– 8b/10b and 64b/66b encoding
– 16-bit, 12-bit, 24-bit and 32-bit formatting
– Subclass 1 multi-device synchronization
• Package: 17-mm × 17-mm FCBGA, 0.8-mm pitch
3 Description
The AFE7700 device is a high-performance,
multichannel transceiver, integrating four direct up-
conversion transmitter chains, four direct down-
conversion receiver chains, and two wideband RF
sampling digitizing auxiliary chains (feedback paths).
The high dynamic range of the transmitter and
receiver chains enables high performance wireless
transceiver systems.
The low power dissipation and large channel
integration of the AFE7700 allows the device to
address the power and size constraints of multi-
antenna and phased array systems. The wideband
and high dynamic range feedback path can assist the
Digital Pre-Distortion (DPD) of power amplifiers and
IQ correction in the transmitter chain. The fast
SerDes speed can reduce the number of lanes
required to transfer the data in and out.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
AFE7700
FCBGA (400)
17.00 mm × 17.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
AFE7700 Block Diagram
2 Applications
Phased Array Radar
Defense Radio
Wireless Communications Test
Vector Signal Transceiver (VST)
Electronic Warfare
VDD1p2TX
VSSTX
1TX+/-
VDD1p8TX
VSSTX
2TX+/-
SYSREF
REFCLK_+/
-
VDD1p8PLL
VSSPLL
3TX+/-
VDD1p8TX
VSSTX
4TX+/-
VDD1p2TX
VSSTX
GPIOs
TX Chain 1
TX Chain 2
From
SPI
DAC
DAC
DAC
DAC
TX Chain 4
From
TX CShaPiIn 3
From SPI
GPIO
DAC
DAC
DAC
DAC
MCU
Config
TX DIG
TX DIG
Common Dig
TX DIG
TX DIG
RF PLL 3
LO
Dist PLL-VCO
RF PLL 4
LO
Dist PLL-VCO
1SRX
1STX
2SRX
2STX
3SRX
3STX
4SRX
4STX
Syncbin/out
5SRX
5STX
6SRX
6STX
7SRX
7STX
8SRX
8STX
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



AFE7700
AFE7700
SLOSE44A – OCTOBER 2019 – REVISED MARCH 2020
www.ti.com
4 Description (continued)
Each receiver chain of the AFE7700 includes a 28-dB range digital step attenuator (DSA), followed by a
wideband passive IQ demodulator, and a baseband amplifier with integrated programmable antialiasing low pass
filters, driving a continuous-time sigma-delta ADC. The RX chain can receive an instantaneous bandwidth (IBW)
up to 200 MHz. Each receiver channel has two analog peak power detectors and various digital power detectors
to assist an external or internal autonomous AGC control for receiver channels, and a RF overload detector for
device reliability protection. The integrated QMC (quadrature mismatch compensation) algorithm is capable to
continuously monitor and correct for the RX chain I and Q imbalance mismatch without the need to inject any
specific signals or perform offline calibration.
Each transmitter chain includes two 14-bit, 3-Gsps IQ DACs, followed by a programmable reconstruction and
DAC image rejection filter, an IQ modulator driving a wideband RF amplifier with 39-dB range gain control. The
TX chain integrated QMC and LO leakage cancellation algorithms, leveraging the FB path can constantly track
and correct for the TX chain IQ mismatch and LO leakage.
Each FB path is based on RF sampling architecture, and includes an input RF DSA driving a 14-bit, 3-Gsps RF
ADC. The direct sampling architecture provides an inherently wideband receiver chain and simplifies the
calibration of the TX chains impairments. The FB path integrates two independent NCO that allows a fast
switching between two observed RF input bands.
The synthesizer section integrates four fractional-N RF PLL that can generate four different RF LO, allowing the
device to support up to two different bands, each one configured as two transmitters, two receivers and one
feedback paths.
spacer
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (October 2019) to Revision A
Page
• Changed the device status From: Advanced Information To: Production Data .................................................................... 1
2 Submit Documentation Feedback
Product Folder Links: AFE7700
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