Analog Front-End. AFE4490 Datasheet

AFE4490 Front-End. Datasheet pdf. Equivalent

Part AFE4490
Description Integrated Analog Front-End
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AFE4490
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AFE4490
SBAS602H – DECEMBER 2012 – REVISED OCTOBER 2014
AFE4490 Integrated Analog Front-End for Pulse Oximeters
1 Features
1 Fully-Integrated Analog Front-End for
Pulse Oximeter Applications:
– Flexible Pulse Sequencing and
Timing Control
• Transmit:
– Integrated LED Driver (H-Bridge, Push, or Pull)
– 110-dB Dynamic Range Across Full Range
(Enables Low Noise at Low LED Current)
– LED Current:
– Programmable Ranges of 50 mA, 75 mA,
100 mA, 150 mA, and 200 mA,
Each with 8-Bit Current Resolution
– Low Power:
– 100 µA + Average LED Current
– LED On-Time Programmability from
(50 µs + Settle Time) to 4 ms
– Independent LED2, LED1 Current Reference
• Receive Channel with High Dynamic Range:
– Input-Referred Noise:
50 pARMS (at 5-µA PD Current)
– 13.5 Noise-Free Bits (at 5-µA PD Current)
– Analog Ambient Cancellation Scheme with
Selectable 1-µA to 10-µA Ambient Current
– Low Power: < 2.3 mW at 3.0-V Supply
– Rx Sample Time: 50 µs to 4 ms
– I-V Amplifier with Seven Separate LED2 and
LED1 Programmable Feedback R and C
Settings
– Integrated Digital Ambient Estimation and
Subtraction
• Integrated Fault Diagnostics:
– Photodiode and LED Open and
Short Detection
– Cable On or Off Detection
• Supplies:
– Rx = 2.0 V to 3.6 V
– Tx = 3.0 V or 5.25 V
• Package: Compact VQFN-40 (6 mm × 6 mm)
• Specified Temperature Range: –40°C to 85°C
2 Applications
• Medical Pulse Oximeter Applications
• Industrial Photometry Applications
3 Description
The AFE4490 is a fully-integrated analog front-end
(AFE) that is ideally suited for pulse-oximeter
applications. The device consists of a low-noise
receiver channel with a 22-bit analog-to-digital
converter (ADC), an LED transmit section, and
diagnostics for sensor and LED fault detection. The
device is a very configurable timing controller. This
flexibility enables the user to have complete control of
the device timing characteristics. To ease clocking
requirements and provide a low-jitter clock to the
device, an oscillator is also integrated that functions
from an external crystal. The device communicates to
an external microcontroller or host processor using an
SPI™ interface.
The device is a complete AFE solution packaged in a
single, compact VQFN-40 package (6 mm × 6 mm)
and is specified over the operating temperature range
of –40°C to 85°C.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
AFE4490
VQFN (40)
6.00 mm × 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
Rx Supply
(2.0 V to 3.6 V)
Rx
+
CPD TIA
+
Stage 2
Gain
Photodiode
Diagnostic
PD Open or Short
Cable Off
LED Open or Short
LED2
AMBLED2
LED1
AMBLED1
+
Buffer
ûADC
Timing
Controller
LED2 Data
Amb (LED2) Data
(LED2 ± Amb) Data
LED1 Data
Amb (LED1) Data
(LED1 ± Amb) Data
AFE
SPI
SPI Interface
LED
Driver
LED
LED Current
Control
DAC
Tx Supply
(3.0 V or 5.25 V)
OSC
8 MHz
AFE
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



AFE4490
AFE4490
SBAS602H – DECEMBER 2012 – REVISED OCTOBER 2014
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 6
6 Pin Configuration and Functions ......................... 6
7 Specifications......................................................... 8
7.1 Absolute Maximum Ratings ...................................... 8
7.2 Handling Ratings....................................................... 8
7.3 Recommended Operating Conditions....................... 9
7.4 Thermal Information .................................................. 9
7.5 Electrical Characteristics......................................... 10
7.6 Timing Requirements: Serial Interface.................... 15
7.7 Supply Ramp and Power-Down Timing
Requirements........................................................... 17
7.8 Typical Characteristics ............................................ 18
8 Detailed Description ............................................ 27
8.1 Overview ................................................................. 27
8.2 Functional Block Diagram ....................................... 27
8.3 Feature Description................................................. 28
8.4 Device Functional Modes........................................ 43
8.5 Programming........................................................... 52
8.6 Register Maps ......................................................... 56
9 Applications and Implementation ...................... 85
9.1 Application Information .......................................... 85
9.2 Typical Application .................................................. 85
10 Power-Supply Recommendations ..................... 90
11 Layout................................................................... 92
11.1 Layout Guidelines ................................................. 92
11.2 Layout Example .................................................... 92
12 Device and Documentation Support ................. 93
12.1 Documentation Support ........................................ 93
12.2 Trademarks ........................................................... 93
12.3 Electrostatic Discharge Caution ............................ 93
12.4 Glossary ................................................................ 93
13 Mechanical, Packaging, and Orderable
Information ........................................................... 93
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (June 2014) to Revision H
Page
• Changed V(ESD) parameter specification values in Absolute Maximum Ratings table ........................................................... 8
• Updated AFE Register Description section to current standards: added legend and bit settings to each bit register ........ 59
Changes from Revision F (October 2013) to Revision G
Page
• Added Applications and Implementation, Power Supply Recommendations, and Layout sections....................................... 1
• Changed sub-bullet of Transmit Features bullet .................................................................................................................... 1
• Changed second sub-bullet of Integrated Fault Diagnostics Features bullet......................................................................... 1
• Changed VCM row in Pin Functions table: changed INM to INN in VCM description ........................................................... 7
• Changed Absolute Maximum Ratings table: changed first five rows and added TXP, TXN pins row ................................... 8
• Added Handling Ratings table ................................................................................................................................................ 8
• Changed I-V Transimpedance Amplifier, VO(shield) parameter: changed test conditions and added minimum and
maximum specifications ...................................................................................................................................................... 11
• Changed Example value for rows t, t2, t4, t5, t7, t11, t13, t15, t17, t19, t22, t24, t26, and t28 in Table 2 ......................................... 36
• Added footnote 2 to Table 2 ................................................................................................................................................. 36
• Added footnote 2 to Figure 63.............................................................................................................................................. 37
• Added footnote 2 to Figure 64.............................................................................................................................................. 38
• Changed INN pin name in Figure 76.................................................................................................................................... 49
• Changed INM to INN throughout Table 3............................................................................................................................. 51
• Added STAGE2EN1 and STG2GAIN1[2:0] in TIAGAIN register ......................................................................................... 57
• Changed STAGE2EN to STAGE2EN2 and STG2GAIN[2:0] to STG2GAIN2[2:0] in TIA_AMB_GAIN register................... 57
• Added last two sentences to NUMAV[7:0] description in CONTROL1: Control Register 1 ................................................. 72
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