DatasheetsPDF.com

loss switch. CBTL02GP023 Datasheet

DatasheetsPDF.com

loss switch. CBTL02GP023 Datasheet






CBTL02GP023 switch. Datasheet pdf. Equivalent




CBTL02GP023 switch. Datasheet pdf. Equivalent





Part

CBTL02GP023

Description

5 Gbps rail-to-rail low insertion loss switch



Feature


.
Manufacture

NXP

Datasheet
Download CBTL02GP023 Datasheet


NXP CBTL02GP023

CBTL02GP023; .


NXP CBTL02GP023

.


NXP CBTL02GP023

.

Part

CBTL02GP023

Description

5 Gbps rail-to-rail low insertion loss switch



Feature


.
Manufacture

NXP

Datasheet
Download CBTL02GP023 Datasheet




 CBTL02GP023
CBTL02GP023
5 Gbps rail-to-rail low insertion loss switch
Rev. 2 — 14 August 2017
Product data sheet
1. General description
The CBTL02GP023 is a one port high performance 5 Gbps rail-to-rail low insertion loss 4x
SPST switch chip optimized to interface USB3.0 signals with high voltage (e.g. USB2
signals) off isolation. It supports 5 Gbps USB3.0 signals and large swing USB2 or UART
signals in dongle or plug applications. It also can be used as a general purpose 5 Gbps
rail-to-rail low insertion loss switch chip in other applications.
The common mode voltage of all the input or output pins have wide common mode range
from 0 V to VDD.
CBTL02GP023 is available in 1.5 mm 2.1 mm 0.32 mm DHX2QFN14 package with
0.4 mm pitch.
2. Features and benefits
One port (two differential channels) 5 Gbps rail-to-rail low insertion loss switch
Differential channels:
Low insertion loss: 1.5 dB at 2.5 GHz; 1 dB at 100 MHz
Low return loss: < 15 dB at 2.5 GHz
Low ON-state resistance: 11 (typ)
Bandwidth: 7 GHz (typ)
Low off-state isolation: 16 dB at 2.5 GHz; 40 dB at 100 MHz
Low DDNEXT crosstalk: < 35 dB at 2.5 GHz and 500 MHz
VIC common mode input voltage: 0 to VDD
Differential input voltage VID: 1.2 V (Max)
Intra-pair skew: 6 ps (typ)
VDD Power Supply voltage range in the dongle or plug:
2.7 V (min) to 3.5 V (max)
Low active current consumption: 500 A (max)
Minimum disable current (ENH = LOW): 12 A (max)
Back current protection on all I/O pins
Patent pending high performance analog pass-gate technology
All channels support rail-to-rail input voltage
Small DHX2QFN14 1.5mm 2.1 mm 0.32 mm package with 0.4 mm pitch
ESD protection exceeds 2000V HBM per JDS-001-2012 and 750 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Operating temperature range: 20 C to +85 C




 CBTL02GP023
NXP Semiconductors
CBTL02GP023
5 Gbps rail-to-rail low insertion loss switch
3. Ordering information
Table 1. Ordering information
Type number
Topside
marking
Package
Name
Description
Version
CBTL02GP023 23
DHX2QFN14 Plastic, super thin quad flat package; no leads; 14
SOT1458-1
terminals; body 1.5 mm x 2.1 mm x 0.32 mm; 0.4 mm pitch
3.1 Ordering options
Table 2. Ordering options
Type number
Orderable
part number
Package
Packing method Minimum
order quantity
CBTL02GP023
CBTL02GP023HOZ DHX2QFN14 REEL 13" Q1/T1 20000
*STANDARD MARK
SBB
Temperature
Tamb = 20 C to +85 C
4. Block diagram
Fig 1. Block diagram
VDD
A1P
A1N
CBTL02GP023
B1N
B1P
ONH
A0P
A0N
B0N
B0P
ENH
GND
aaa-025204
CBTL02GP023
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 14 August 2017
© NXP Semiconductors N.V. 2017. All rights reserved.
2 of 19




 CBTL02GP023
NXP Semiconductors
5. Pinning information
5.1 Pinning
CBTL02GP023
5 Gbps rail-to-rail low insertion loss switch
CBTL02GP023
GND 14
GND 1
GND
8 VDD
7 ENH
terminal 1
index area
Fig 2. Pin configuration (top view)
aaa-025205
Refer to Section 10 “Package outline” for package related information.
5.2 Pin description
Table 3. Pin description
Symbol
Pin Type
Description
Data path signals
A1P 3 differential I/O USB3.0 differential signals for A port
A1N 4 differential I/O
A0N 12 differential I/O USB3.0 differential signals for A port (P and N is
A0P 11 differential I/O crossed for A port)
B1N 5 differential I/O USB3.0 differential signals for B port
B1P 6 differential I/O
B0N 10 differential I/O USB3.0 differential signals for B port (P and N is a flow
B0P 9 differential I/O through differential path for B port)
Control signal
ENH
7 control input When HIGH, enables switches. When LOW, whole
chip is powered down
ONH
13 control input When HIGH, all switches are turned on. When LOW,
all switches are OFF, but the control circuit is still
working to improve isolation performance
Power supply
VDD
8 power
Power supply range between 2.7 V and 3.5 V
Ground connection
GND
1, 2, 14, ground
center
pad
0V
CBTL02GP023
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 14 August 2017
© NXP Semiconductors N.V. 2017. All rights reserved.
3 of 19



Recommended third-party CBTL02GP023 Datasheet






@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)