AD9201

a FEATURES Complete Dual Matching ADCs Low Power Dissipation: 215 mW (+3 V Supply) Single Supply: 2.7 V to 5.5 V Differential Nonlinearity Error: 0.4 LSB On-Chip Analog Input Buffers On-Chip Reference Signal-to-Noise Ratio: 57.8 dB Over Nine Effective Bits Spurious-Free Dynamic Range: –73 dB No Missing Codes Guaranteed 28-Lead SSOP Dual Channel, 20 MHz 10-Bit Resolution CMOS ADC AD9201 FUNCTIONAL BLOCK DIAGRAM AVDD IINA IINB IREFB IREFT QREFB QREFT VREF REFSENSE QINB QINA "Q" ADC Q REGISTER REFERENCE BUFFER ASYNCHRONOUS MULTIPLEXER 1V CHIP SELECT THREESTATE OUTPUT BUFFER DATA 10 BITS AVSS CLOCK DVDD DVSS "I" ADC I REGISTER AD9201 SLEEP SELECT PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD9201 is a complete dual channel, 20 MSPS, 10-bit CMOS ADC. The AD9201 is optimized specifically for applications where close matching between two ADCs is required (e.g., I/Q channels in communications applications). The 20 MHz sampling rate and wide input bandwidth will cover both narrowband and spread-spectrum channels. The AD9201 integrates two 10-bit, 20 MSPS ADCs, two input buffer amplifiers, an internal voltage reference and multiplexed digital output buffers. Each ADC incorporates a simultaneous sampling sample-andhold amplifier at its input. The analog inputs are buffered; no external input buffer op amp will be required in most applications. The ADCs are implemented using a multistage pipeline architecture that offers accurate performance and guarantees no missing codes. The outp...