CTL0212PS-R3

CTL0212PS-R3 P-Channel Enhancement MOSFET Features  Drain-Source Breakdown Voltage VDSS -20 V  Drain-Source On-Resistance RDS(ON) 130m, at VGS= -4.5V, ID= -1.0A RDS(ON) 140m, at VGS= -2.5V, ID= -0.5A  Continuous Drain Current at TC=25℃ID = -2.1A  Advanced high cell density Trench Technology  RoHS Compliance & Halogen Free Applications  Power Management  Lithium Ion Battery Description The CTL0212PS-R3 is the P-Channel logic enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook computer power management and other battery powered circuits ,and low in-line power loss are needed in a very small outline surface mount package. Package Outline Schematic Drain Gate Source Drain Gate Source CT Micro Proprietary & Confidential Page 1 Rev 1 Nov, 2013 CTL0212PS-R3 P-Channel Enhancement MOSFET Absolute Maximum Rating at 25oC Symbol Parameters VDS Drain-Source Voltage VGS Gate-Source Voltage ID Continuous Drain Current IDM Pulsed Drain Current PD Total Power Dissipation TSTG Storage Temperature Range TJ Operating Junction Temperature Range Thermal Characteristics Symbol Parameters RӨJA4 Thermal Resistance Junction-Ambient (t=10s) Test Conditions Test Conditions -20 ±8 -2.1 -9 1.3 -55 to 150 -55 to 150 Min Notes V V...